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modified post dd10c by Anonymous on Fri 30th Nov 2018 15:26
original post fec8ec8 by Anonymous on Wed 28th Nov 2018 15:41
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1-
Index: /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1283853740.patch
1+
Index: /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1330436059.patch
22
===================================================================
3-
--- /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1283853740.patch	(Revision 2781)
3+
--- /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1330436059.patch (Revision 0)
4-
+++ /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1283853740.patch	(Revision 2782)
4+
+++ /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1330436059.patch (Revision 2782)
5-
@@ -194,7 +194,7 @@
5+
@@ -0,0 +1,57 @@
6-
 +#define LCDC_LSCR 0x00120300
6+
+diff --exclude CVS --exclude .git -uNr u-boot-2009.08/board/freescale/quantron_a/quantron_a.c u-boot-2009.08.modified/board/freescale/quantron_a/quantron_a.c
7-
 +#define LCDC_LRMCR 0x00000000
7+
+--- u-boot-2009.08/board/freescale/quantron_a/quantron_a.c     2012-02-28 14:34:25.000000000 +0100
8-
 +#define LCDC_LDCR 0x00020010
8+
++++ u-boot-2009.08.modified/board/freescale/quantron_a/quantron_a.c    2012-02-28 14:26:18.000000000 +0100
9-
-+#define LCDC_LPCCR 0x00a9037f
9+
+@@ -168,6 +168,45 @@
10-
++#define LCDC_LPCCR 0x00a903ff
10+
+ int board_init(void)
11-
 +#define LCDC_LPCR 0xFA008B80
11+
+ {
12-
 +#define LCDC_LPCR_PCD 0x4
12+
+       setup_soc_rev();
13-
 +
13+
++
14-
Index: /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/kernel-2.6.31-1327402865.patch.md5
14+
++         mxc_iomux_set_pad(MX25_PIN_PWM, PAD_CTL_PKE_ENABLE |
15-
===================================================================
15+
++              PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
16-
--- /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/kernel-2.6.31-1327402865.patch.md5	(Revision 0)
16+
++
17-
+++ /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/kernel-2.6.31-1327402865.patch.md5	(Revision 2782)
17+
++
18-
@@ -0,0 +1 @@
18+
++         mxc_iomux_set_pad(MX25_PIN_PWM, PAD_CTL_PKE_ENABLE |
19-
+2baf10b6bf67f4c0f2d3cca766b2e8e8  ./freescale/pkgs/kernel-2.6.31-1327402865.patch
19+
++              PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
20-
Index: /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1330436059.patch
20+
++
21-
===================================================================
21+
++         mxc_request_iomux(MX25_PIN_CSI_HSYNC, MUX_CONFIG_ALT5);
22-
--- /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1330436059.patch	(Revision 0)
22+
++         mxc_iomux_set_pad(MX25_PIN_CSI_HSYNC, PAD_CTL_PKE_ENABLE |
23-
+++ /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1330436059.patch	(Revision 2782)
23+
++                                PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
24-
@@ -0,0 +1,57 @@
24+
++       mxc_set_gpio_dataout(MX25_PIN_CSI_HSYNC, 0);
3225
++
33-
++         mxc_iomux_set_pad(MX25_PIN_PWM, PAD_CTL_PKE_ENABLE |
26+
++         mxc_request_iomux(MX25_PIN_CSPI1_RDY, MUX_CONFIG_ALT5);
34-
++              PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
27+
++         mxc_iomux_set_pad(MX25_PIN_CSPI1_RDY, PAD_CTL_PKE_ENABLE |
28+
++                                PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
3530
++
31+
++         mxc_request_iomux(MX25_PIN_UART2_CTS, MUX_CONFIG_ALT5);
3636
++
37-
++         mxc_iomux_set_pad(MX25_PIN_PWM, PAD_CTL_PKE_ENABLE |
37+
++         mxc_request_iomux(MX25_PIN_CSI_MCLK, MUX_CONFIG_ALT5);
38-
++              PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
38+
++         mxc_iomux_set_pad(MX25_PIN_CSI_MCLK, PAD_CTL_PKE_ENABLE |
39+
++                                PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
3941
++
40-
++         mxc_request_iomux(MX25_PIN_CSI_HSYNC, MUX_CONFIG_ALT5);
42+
++         mxc_request_iomux(MX25_PIN_CSI_VSYNC, MUX_CONFIG_ALT5);
41-
++         mxc_iomux_set_pad(MX25_PIN_CSI_HSYNC, PAD_CTL_PKE_ENABLE |
43+
++         mxc_iomux_set_pad(MX25_PIN_CSI_VSYNC, PAD_CTL_PKE_ENABLE |
42-
++				  PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
44+
++                                PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
43-
++	 mxc_set_gpio_dataout(MX25_PIN_CSI_HSYNC, 0);
45+
++      mxc_set_gpio_dataout(MX25_PIN_CSI_VSYNC, 0);
4446
++
45-
++         mxc_request_iomux(MX25_PIN_CSPI1_RDY, MUX_CONFIG_ALT5);
47+
++         mxc_request_iomux(MX25_PIN_CSI_D8, MUX_CONFIG_ALT5);
46-
++         mxc_iomux_set_pad(MX25_PIN_CSPI1_RDY, PAD_CTL_PKE_ENABLE |
48+
++         mxc_iomux_set_pad(MX25_PIN_CSI_D8, PAD_CTL_PKE_ENABLE |
47-
++				  PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
49+
++                                PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
48-
++	 mxc_set_gpio_dataout(MX25_PIN_CSPI1_RDY, 0);
50+
++      mxc_set_gpio_dataout(MX25_PIN_CSI_D8, 0);
49-
++
51+


50-
++         mxc_request_iomux(MX25_PIN_UART2_CTS, MUX_CONFIG_ALT5);


52+


51-
++         mxc_iomux_set_pad(MX25_PIN_UART2_CTS, PAD_CTL_PKE_ENABLE |


53+


52-
++				  PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);


54+


53-
++	 mxc_set_gpio_direction(MX25_PIN_UART2_CTS, 0);           /* Als Ausgang definieren */


55+


54-
++	 mxc_set_gpio_dataout(MX25_PIN_UART2_CTS, 0);


56+


55-
++


57+


56-
++         mxc_request_iomux(MX25_PIN_CSI_MCLK, MUX_CONFIG_ALT5);


58+


57-
++         mxc_iomux_set_pad(MX25_PIN_CSI_MCLK, PAD_CTL_PKE_ENABLE |


59+


58-
++				  PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);


60+


59-
++	mxc_set_gpio_dataout(MX25_PIN_CSI_MCLK, 0);


61+


60-
++


62+


61-
++         mxc_request_iomux(MX25_PIN_CSI_VSYNC, MUX_CONFIG_ALT5);


63+


62-
++         mxc_iomux_set_pad(MX25_PIN_CSI_VSYNC, PAD_CTL_PKE_ENABLE |


64+


63-
++				  PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);


65+


64-
++	mxc_set_gpio_dataout(MX25_PIN_CSI_VSYNC, 0);


66+


65-
++


67+


66-
++         mxc_request_iomux(MX25_PIN_CSI_D8, MUX_CONFIG_ALT5);


68+


67-
++         mxc_iomux_set_pad(MX25_PIN_CSI_D8, PAD_CTL_PKE_ENABLE |


69+


68-
++				  PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);


70+


69-
++	mxc_set_gpio_dataout(MX25_PIN_CSI_D8, 0);


71+


70-
++


72+


71-
+ 	/* setup pins for UART5 */


73+


72-
+ 	/* UART 5 IOMUX Configs */


74+


73-
+          mxc_request_iomux(MX25_PIN_PWM, MUX_CONFIG_FUNC);


75+


74-
+@@ -187,6 +226,7 @@


76+


75-
+                         INPUT_CTL_PATH1);


77+


76-
+


78+


77-
+


79+


78-
++


80+


79-
+ 	/* setup pins for FEC */


81+


80-
+ 	mxc_request_iomux(MX25_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);


82+


81-
+ 	mxc_request_iomux(MX25_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);


83+


82-
Index: /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1283853740.patch.md5


84+


83-
===================================================================


85+


84-
--- /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1283853740.patch.md5	(Revision 2781)


86+


85-
+++ /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1283853740.patch.md5	(Revision 2782)


87+


86-
@@ -1 +1 @@


88+


87-
-24cb90163505e390889987c5f9a6d203  u-boot-2009.08-1283853740.patch


89+


88-
+419a5f9f6301998ff199bf8c44f8aceb  ./freescale/pkgs/u-boot-2009.08-1283853740.patch


90+


89-
Index: /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1330436059.patch.md5


91+


90-
===================================================================


92+


91-
--- /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1330436059.patch.md5	(Revision 0)


93+


92-
+++ /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1330436059.patch.md5	(Revision 2782)


94+


93-
@@ -0,0 +1 @@


95+


94-
+1b853c6f4860feecbf74398cf024163e  ./freescale/pkgs/u-boot-2009.08-1330436059.patch


96+


95-
Index: /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/kernel-2.6.31-1327402865.patch


97+


96-
===================================================================


98+


97-
--- /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/kernel-2.6.31-1327402865.patch	(Revision 0)


99+


98-
+++ /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/kernel-2.6.31-1327402865.patch	(Revision 2782)


100+


99-
@@ -0,0 +1,511 @@


101+


100-
+diff --exclude CVS --exclude .git -uNr linux-2.6.31/arch/arm/mach-mx25/mx25_qa.c linux-2.6.31.modified/arch/arm/mach-mx25/mx25_qa.c


102+


101-
+--- linux-2.6.31/arch/arm/mach-mx25/mx25_qa.c	2012-02-27 12:12:26.000000000 +0100


103+


102-
++++ linux-2.6.31.modified/arch/arm/mach-mx25/mx25_qa.c	2012-02-27 11:53:00.000000000 +0100


104+


103-
+@@ -346,10 +346,14 @@


105+


104-
+


106+


105-
+ static void __init mx25_qa_timer_init(void)


107+


106-
+ {


108+


107-
++   /* Clock source fuer den gpt ist ahb_div */


109+


108-
++   __raw_writel(__raw_readl(MXC_CCM_BASE+0x64) & ~(1 << 5),


110+


109-
++                MXC_CCM_BASE + 0x64);


111+


110-
++


112+


111-
+ 	mx25_clocks_init(24000000);


113+


112-
+ }


114+


113-
+


115+


114-
+-static struct sys_timer mxc_timer = {


116+


115-
++static struct sys_timer mxc_timer = {


117+


116-
+    .init	= mx25_qa_timer_init,


118+


117-
+ };


119+


118-
+


120+


119-
+diff --exclude CVS --exclude .git -uNr linux-2.6.31/drivers/mxc/adc/imx_adc.c linux-2.6.31.modified/drivers/mxc/adc/imx_adc.c


121+


120-
+--- linux-2.6.31/drivers/mxc/adc/imx_adc.c	2012-01-24 12:01:56.000000000 +0100


122+


121-
++++ linux-2.6.31.modified/drivers/mxc/adc/imx_adc.c	2012-01-24 11:55:41.000000000 +0100


123+


122-
+@@ -48,6 +48,17 @@


124+


123-
+ static int suspend_flag;


125+


124-
+


126+


125-
+ /*!


127+


126-
++ * To indicate that the touchscreen was touched at least one time


128+


127-
++ */


129+


128-
++static bool touched = false;


130+


129-
++


131+


130-
++/*!


132+


131-
++ * The time in ms to wait between reading the ADCStatus Flag


133+


132-
++ * while the screen wasn't touched since last boot up


134+


133-
++ */


135+


134-
++#define ADC_STATUS_READING_GAP      300


136+


135-
++


137+


136-
++/*!


138+


137-
+  * The suspendq is used by blocking application calls


139+


138-
+  */


140+


139-
+ static wait_queue_head_t suspendq;


141+


140-
+@@ -285,8 +296,17 @@


142+


141-
+ 		__raw_writel(reg, tsc_base + TCQMR);


143+


142-
+


144+


143-
+ 		wait_event_interruptible(tsq, ts_data_ready);


145+


144-
+-		while (!(__raw_readl(tsc_base + TCQSR) & CQSR_EOQ))


146+


145-
++


147+


146-
++		while (!(__raw_readl(tsc_base + TCQSR) & CQSR_EOQ)){


148+


147-
++


149+


148-
++			// When the screen was not touched since bootup, wait a bit


150+


149-
++			// otherwise this "while" would run full powered until the


151+


150-
++			// screen is touched.


152+


151-
++			if (!touched) {


153+


152-
++			msleep(ADC_STATUS_READING_GAP);


154+


153-
++			}


155+


154-
+ 			continue;


156+


155-
++		}


157+


156-
+ 		/* stop the conversion */


158+


157-
+ 		reg = __raw_readl(tsc_base + TCQCR);


159+


158-
+ 		reg &= ~CQCR_QSM_MASK;


160+


159-
+@@ -370,6 +390,10 @@


161+


160-
+


162+


161-
+ 	if (tsi_data == FQS_DATA)


163+


162-
+ 		up(&ts_convert_mutex);


164+


163-
++


165+


164-
++	/* Now we know that the touchscreen was touched at least one time */


166+


165-
++	touched = true;


167+


166-
++


168+


167-
+ 	return IMX_ADC_SUCCESS;


169+


168-
+ }


170+


169-
+


171+


170-
+diff --exclude CVS --exclude .git -uNr linux-2.6.31/drivers/video/mxc/mx2fb.c linux-2.6.31.modified/drivers/video/mxc/mx2fb.c


172+


171-
+--- linux-2.6.31/drivers/video/mxc/mx2fb.c	2012-01-24 12:01:57.000000000 +0100


173+


172-
++++ linux-2.6.31.modified/drivers/video/mxc/mx2fb.c	2012-01-24 11:23:35.000000000 +0100


174+


173-
+@@ -1086,7 +1086,7 @@


175+


174-
+ void mx2fb_set_brightness(uint8_t level)


176+


175-
+ {


177+


176-
+ 	/* Set LCDC PWM contract control register */


178+


177-
+-	__raw_writel(0x00A90300 | level, LCDC_REG(LCDC_LPCCR));


179+


178-
++	__raw_writel(0, LCDC_REG(LCDC_LPCCR));


180+


179-
+ }


181+


180-
+


182+


181-
+ EXPORT_SYMBOL(mx2fb_set_brightness);


183+


182-
+


184+


183-
+diff --exclude CVS --exclude .git -uNr linux-2.6.31/arch/arm/mach-mx25/clock.c linux-2.6.31.modified/arch/arm/mach-mx25/clock.c


185+


184-
+--- linux-2.6.31/arch/arm/mach-mx25/clock.c	2011-04-12 11:03:01.000000000 +0200


186+


185-
++++ linux-2.6.31.modified/arch/arm/mach-mx25/clock.c	2011-04-05 11:48:32.000000000 +0200


187+


186-
+@@ -1746,6 +1746,6 @@


188+


187-
+    clk_enable(&gpt3_clk[1]);


189+


188-
+    clk_enable(&gpt4_clk[1]);


190+


189-
+


191+


190-
+-	mxc_timer_init(&gpt1_clk[0], IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1);


192+


191-
++	mxc_timer_init(&gpt1_clk[0], IO_ADDRESS(GPT3_BASE_ADDR), MXC_INT_GPT3);


193+


192-
+ 	return 0;


194+


193-
+ }


195+


194-
+diff --exclude CVS --exclude .git -uNr linux-2.6.31/arch/arm/mach-mx25/devices.c linux-2.6.31.modified/arch/arm/mach-mx25/devices.c


196+


195-
+--- linux-2.6.31/arch/arm/mach-mx25/devices.c	2011-04-12 11:03:02.000000000 +0200


197+


196-
++++ linux-2.6.31.modified/arch/arm/mach-mx25/devices.c	2011-04-05 11:27:36.000000000 +0200


198+


197-
+@@ -560,15 +560,21 @@


199+


198-
+ 	      .flags = IORESOURCE_MEM,


200+


199-
+ 	},


201+


200-
+


202+


201-
+-	[2] = {


203+


202-
+-	      .start = GPT3_BASE_ADDR,


204+


203-
+-	      .end = GPT3_BASE_ADDR + SZ_4K - 1,


205+


204-
+-	      .flags = IORESOURCE_MEM,


206+


205-
++   [2] = {


207+


206-
++         .start = GPT1_BASE_ADDR,


208+


207-
++         .end = GPT1_BASE_ADDR + SZ_4K - 1,


209+


208-
++         .flags = IORESOURCE_MEM,


210+


209-
+    },


211+


210-
+


212+


211-
+ 	[3] = {


213+


212-
++	      .start = GPT2_BASE_ADDR,


214+


213-
++	      .end = GPT2_BASE_ADDR + SZ_4K - 1,


215+


214-
++	      .flags = IORESOURCE_MEM,


216+


215-
++   },


217+


216-
++


218+


217-
++	[4] = {


219+


218-
+ 	      .start = GPT4_BASE_ADDR,


220+


219-
+-	      .end = GPT4_BASE_ADDR + SZ_4K - 1,


221+


220-
++	      .end = GPT4_BASE_ADDR + SZ_4K - 1,


222+


221-
+ 	      .flags = IORESOURCE_MEM,


223+


222-
+ 	},


224+


223-
+


225+


224-
+


226+


225-
+


227+


226-
+


228+


227-
+


229+


228-
+diff --exclude CVS --exclude .git -uNr linux-2.6.31/arch/arm/mach-mx25/mx25_qa_gpio.c linux-2.6.31.modified/arch/arm/mach-mx25/mx25_qa_gpio.c


230+


229-
+--- linux-2.6.31/arch/arm/mach-mx25/mx25_qa_gpio.c	2011-04-12 11:03:02.000000000 +0200


231+


230-
++++ linux-2.6.31.modified/arch/arm/mach-mx25/mx25_qa_gpio.c	2011-04-05 09:18:26.000000000 +0200


232+


231-
+@@ -358,40 +358,41 @@


233+


232-
+ }


234+


233-
+ EXPORT_SYMBOL(gpio_pwm_inactive);


235+


234-
+


236+


235-
+-void gpio_cc_active(int cc_nr){


237+


236-
++void gpio_cc_active(void){


238+


237-
+    /*


239+


238-
+     * Configure the IOMUX control registers for the compare capture signals


240+


239-
+     */


241+


240-
+-   switch ( cc_nr ) {


242+


241-
+-      case 0:


243+


242-
+-         /* CC3 IOMUX Configs */


244+


243-
+-         mxc_request_iomux(MX25_PIN_UART1_RTS, MUX_CONFIG_ALT2);


245+


244-
+-         mxc_iomux_set_pad(MX25_PIN_UART1_RTS, PAD_CTL_47K_PU);


246+


245-
+-         break;


247+


246-
+-      case 1:


248+


247-
+-         /* CC4 IOMUX Configs */


249+


248-
+-         mxc_request_iomux(MX25_PIN_CONTRAST, MUX_CONFIG_ALT1);


250+


249-
+-         mxc_iomux_set_pad(MX25_PIN_CONTRAST, PAD_CTL_47K_PU);


251+


250-
+-         break;


252+


251-
+-      default:


253+


252-
+-         break;


254+


253-
+-   }


255+


254-
++   /* CC3 IOMUX Configs */


256+


255-
++   mxc_request_iomux(MX25_PIN_UART1_RTS, MUX_CONFIG_ALT2);


257+


256-
++   mxc_iomux_set_pad(MX25_PIN_UART1_RTS, PAD_CTL_47K_PU);


258+


257-
++


259+


258-
++   mxc_request_iomux(MX25_PIN_CONTRAST, MUX_CONFIG_ALT1);


260+


259-
++   mxc_iomux_set_pad(MX25_PIN_CONTRAST, PAD_CTL_47K_PU);


261+


260-
++


262+


261-
++   mxc_request_iomux(MX25_PIN_GPIO_C, MUX_CONFIG_ALT4);


263+


262-
++   mxc_iomux_set_pad(MX25_PIN_GPIO_C, PAD_CTL_47K_PU);


264+


263-
++


265+


264-
++   mxc_request_iomux(MX25_PIN_UART2_RTS, MUX_CONFIG_ALT3);


266+


265-
++   mxc_iomux_set_pad(MX25_PIN_UART2_RTS, PAD_CTL_47K_PU);


267+


266-
++


268+


267-
+ }


269+


268-
+ EXPORT_SYMBOL(gpio_cc_active);


270+


269-
+


271+


270-
+-void gpio_cc_inactive(int cc_nr){


272+


271-
+-   switch ( cc_nr ) {


273+


272-
+-      case 0:


274+


273-
+-         gpio_request(IOMUX_TO_GPIO(MX25_PIN_UART1_RTS), NULL);


275+


274-
+-         mxc_free_iomux(MX25_PIN_UART1_RTS, MUX_CONFIG_GPIO);


276+


275-
+-         break;


277+


276-
+-      case 1:


278+


277-
+-         mxc_free_iomux(MX25_PIN_CONTRAST, MUX_CONFIG_FUNC);


279+


278-
+-         break;


280+


279-
+


281+


280-
+-      default:


282+


281-
+-         break;


283+


282-
+-   }


284+


283-
++void gpio_cc_inactive(void){


285+


284-
++


286+


285-
++   gpio_request(IOMUX_TO_GPIO(MX25_PIN_UART1_RTS), NULL);


287+


286-
++   mxc_free_iomux(MX25_PIN_UART1_RTS, MUX_CONFIG_GPIO);


288+


287-
++


289+


288-
++   mxc_free_iomux(MX25_PIN_CONTRAST, MUX_CONFIG_FUNC);


290+


289-
++


291+


290-
++   gpio_request(IOMUX_TO_GPIO(MX25_PIN_GPIO_C), NULL);


292+


291-
++   mxc_free_iomux(MX25_PIN_GPIO_C, MUX_CONFIG_GPIO);


293+


292-
++


294+


293-
++   gpio_request(IOMUX_TO_GPIO(MX25_PIN_UART2_RTS), NULL);


295+


294-
++   mxc_free_iomux(MX25_PIN_UART2_RTS, MUX_CONFIG_GPIO);


296+


295-
++


297+


296-
++


298+


297-
+ }


299+


298-
+ EXPORT_SYMBOL(gpio_cc_inactive);


300+


299-
+


301+


300-
+diff --exclude CVS --exclude .git -uNr linux-2.6.31/arch/arm/plat-mxc/include/mach/mxc_timer.h linux-2.6.31.modified/arch/arm/plat-mxc/include/mach/mxc_timer.h


302+


301-
+--- linux-2.6.31/arch/arm/plat-mxc/include/mach/mxc_timer.h	2011-04-12 11:02:52.000000000 +0200


303+


302-
++++ linux-2.6.31.modified/arch/arm/plat-mxc/include/mach/mxc_timer.h	2011-04-05 11:39:36.000000000 +0200


304+


303-
+@@ -67,8 +67,8 @@


305+


304-
+ }


306+


305-
+


307+


306-
+ #elif defined(CONFIG_ARCH_MX2)


308+


307-
+-#define TIMER_BASE		IO_ADDRESS(GPT1_BASE_ADDR)


309+


308-
+-#define TIMER_INTERRUPT		MXC_INT_GPT1


310+


309-
++#define TIMER_BASE		IO_ADDRESS(GPT3_BASE_ADDR)


311+


310-
++#define TIMER_INTERRUPT		MXC_INT_GPT3


312+


311-
+


313+


312-
+ #define MXC_TCTL   0x00


314+


313-
+ #define TCTL_VAL		TCTL_CLK_PCLK1


315+


314-
+diff --exclude CVS --exclude .git -uNr linux-2.6.31/arch/arm/plat-mxc/time.c linux-2.6.31.modified/arch/arm/plat-mxc/time.c


316+


315-
+--- linux-2.6.31/arch/arm/plat-mxc/time.c	2011-04-12 11:02:52.000000000 +0200


317+


316-
++++ linux-2.6.31.modified/arch/arm/plat-mxc/time.c	2011-04-05 11:37:00.000000000 +0200


318+


317-
+@@ -59,6 +59,83 @@


319+


318-
+ #define MX3_TCMP		0x10


320+


319-
+


321+


320-
+ #define timer_is_v2()	(!(cpu_is_mx1() || cpu_is_mx2()) || cpu_is_mx25())


322+


321-
++/* Anzahl der CC-Kanaele */


323+


322-
++#define SPEED_CHANNELS          		((uchar)  2 )


324+


323-
++


325+


324-
++


326+


325-
++#define SPEED_DEF_PRESC        		((ushort) 664   )


327+


326-
++


328+


327-
++/* CC vituelle Adressen Register */


329+


328-
++#define GPTCR(x)             		(((ulong *) x)+0 )


330+


329-
++#define GPTPR(x)             		(((ulong *) x)+1 )


331+


330-
++#define GPTSR(x)             		(((ulong *) x)+2 )


332+


331-
++#define GPTIR(x)            		(((ulong *) x)+3 )


333+


332-
++#define GPTICR1(x)           		(((ulong *) x)+7 )


334+


333-
++#define GPTICR2(x)           		(((ulong *) x)+8 )


335+


334-
++#define GPTCNT(x)            		(((ulong *) x)+9 )


336+


335-
++


337+


336-
++


338+


337-
++/// PWM Bits


339+


338-
++#define GPT_IM2(x)    		      ((ulong) ((uchar)x<<18))


340+


339-
++#define GPT_IM1(x)      		   ((ulong) ((uchar)x<<16))


341+


340-
++#define GPT_SWR             		((ulong) 1<<15)


342+


341-
++#define GPT_FRR           	   	((ulong) 1<<9)


343+


342-
++#define GPT_CLKSRC(x) 		      ((ulong) ((uchar)x<<6))


344+


343-
++#define GPT_STOPEN         		((ulong) 1<<5)


345+


344-
++#define GPT_WAITEN          		((ulong) 1<<3)


346+


345-
++#define GPT_ENMOD         		   ((ulong) 1<<1)


347+


346-
++#define GPT_EN         		      ((ulong) 1<<0)


348+


347-
++


349+


348-
++#define GPT_ROVIE    		      ((ulong) 1<<5)


350+


349-
++#define GPT_IF2IE         		   ((ulong) 1<<4)


351+


350-
++#define GPT_IF1IE     		      ((ulong) 1<<3)


352+


351-
++


353+


352-
++#define GPT_ROV        		      ((ulong) 1<<5)


354+


353-
++#define GPT_IF2         		   ((ulong) 1<<4)


355+


354-
++#define GPT_IF1        		      ((ulong) 1<<3)


356+


355-
++#define GPT_OF1        		      ((ulong) 1<<0)


357+


356-
++


358+


357-
++#define GPT_CLKSRC_OFF        	((ulong) 0<<6)


359+


358-
++#define GPT_CLKSRC_IPG        	((ulong) 1<<6)


360+


359-
++#define GPT_CLKSRC_IPG_HF     	((ulong) 2<<6)


361+


360-
++#define GPT_CLKSRC_IND_CLKIN   	((ulong) 3<<6)


362+


361-
++#define GPT_CLKSRC_IPG_32K    	((ulong) 4<<6)


363+


362-
++


364+


363-
++#define SPEED_NO_EVENT				   0


365+


364-
++


366+


365-
++


367+


366-
++#define SPEED            				0


368+


367-
++


369+


368-
++


370+


369-
++#define SPEED_HIGH_EDGE		         0


371+


370-
++#define SPEED_LOW_EDGE		         1


372+


371-
++


373+


372-
++/*******************************************************************************


374+


373-
++@Typdefinitionen (modullokal)


375+


374-
++*******************************************************************************/


376+


375-
++


377+


376-
++/*******************************************************************************


378+


377-
++@Variablen (modullokal)


379+


378-
++*******************************************************************************/


380+


379-
++


381+


380-
++


382+


381-
++/* Virtuelle Adresse fuer die PWM Resourcen */


383+


382-
++volatile static ulong *paulSPEED_virtualbase;


384+


383-
++


385+


384-
++/* Capture Values 1 */


386+


385-
++volatile static u32 aulSPEED_Val;


387+


386-
++


388+


387-
++/* Capture Values Channel 1 */


389+


388-
++volatile static u32 aulSPEED_Val1[2];


390+


389-
++


391+


390-
++/* old Capture Values */


392+


391-
++volatile static u32 aulSPEED_Val_Old;


393+


392-
++


394+


393-
++/* Capture Status */


395+


394-
++volatile static u8 aucSPEED_Stat;


396+


395-
++


397+


396-
++/* Toggle Bit */


398+


397-
++volatile static u8 aucSPEED_Toggle;


399+


398-
+


400+


399-
+ static struct clock_event_device clockevent_mxc;


401+


400-
+ static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;


402+


401-
+@@ -79,8 +156,10 @@


403+


402-
+


404+


403-
+ static inline void gpt_irq_enable(void)


405+


404-
+ {


406+


405-
+-	if (timer_is_v2())


407+


406-
+-		__raw_writel(1<<0, timer_base + MX3_IR);


408+


407-
++	if (timer_is_v2()) {


409+


408-
++		__raw_writel(0x09, timer_base + MX3_IR);


410+


409-
++       printk("mxc_set_mo\n\n\n\n\n\n");


411+


410-
++   }


412+


411-
+ 	else {


413+


412-
+ 		__raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,


414+


413-
+ 			timer_base + MXC_TCTL);


415+


414-
+@@ -94,7 +173,7 @@


416+


415-
+ 	if (cpu_is_mx2())


417+


416-
+ 		__raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, timer_base + MX1_2_TSTAT);


418+


417-
+ 	if (timer_is_v2())


419+


418-
+-		__raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT);


420+


419-
++		__raw_writel(0x09, timer_base + MX3_TSTAT);


421+


420-
+ }


422+


421-
+


423+


422-
+ static cycle_t mx1_2_get_cycles(struct clocksource *cs)


424+


423-
+@@ -234,20 +313,157 @@


425+


424-
+ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)


426+


425-
+ {


427+


426-
+ 	struct clock_event_device *evt = &clockevent_mxc;


428+


427-
+-	uint32_t tstat;


429+


428-
++   ulong ulCap_Val=0;


430+


429-
++   ulong ulStatus;


431+


430-
+


432+


431-
+-	if (timer_is_v2())


433+


432-
+-		tstat = __raw_readl(timer_base + MX3_TSTAT);


434+


433-
+-	else


435+


434-
+-		tstat = __raw_readl(timer_base + MX1_2_TSTAT);


436+


435-
++   ulStatus = __raw_readl(timer_base + MX3_TSTAT);


437+


436-
++   gpt_irq_acknowledge();


438+


437-
++


439+


438-
++


440+


439-
++   if(ulStatus & GPT_IF1){


441+


440-
++      ulCap_Val =  __raw_readl(timer_base + 0x1C);


442+


441-
++


443+


442-
++


444+


443-
++      /* Wenn ein Timerueberlauf stattgefunden hat */


445+


444-
++      if( (ulStatus & GPT_IF1)  && (ulCap_Val < aulSPEED_Val_Old) ){


446+


445-
++


447+


446-
++         /* Capture-Werte < 10 werden nicht beruecksichtigt */


448+


447-
++         if( ( (0xFFFFFFFF - aulSPEED_Val_Old) + ulCap_Val) > 10){


449+


448-
++            /* abwechselnd Werte fuer High und Lowedge schreiben */


450+


449-
++            aucSPEED_Toggle = (aucSPEED_Toggle+1)&0x01;


451+


450-
++            aulSPEED_Val1[aucSPEED_Toggle] = (0xFFFFFFFF - aulSPEED_Val_Old) + ulCap_Val;


452+


451-
++


453+


452-
++            /* den alten Capturewert behalten*/


454+


453-
++            aulSPEED_Val_Old = ulCap_Val;


455+


454-
++         }


456+


455-
++


457+


456-
++      }


458+


457-
++


459+


458-
++      /* Wenn kein Timerueberlauf stattgefunden hat */


460+


459-
++      if( (ulStatus & GPT_IF1) &&(ulCap_Val > aulSPEED_Val_Old) ){


461+


460-
++


462+


461-
++         /* Capture-Werte < 10 werden nicht beruecksichtigt */


463+


462-
++         if( (ulCap_Val - aulSPEED_Val_Old) > 10){


464+


463-
+


465+


464-
+-	gpt_irq_acknowledge();


466+


465-
++            /* abwechselnd Werte fuer High und Lowedge schreiben */


467+


466-
++            aucSPEED_Toggle = (aucSPEED_Toggle+1)&0x01;


468+


467-
++            aulSPEED_Val1[aucSPEED_Toggle] = ulCap_Val - aulSPEED_Val_Old;


469+


468-
+


470+


469-
+-	evt->event_handler(evt);


471+


470-
++            /* den alten Capturewert behalten*/


472+


471-
++            aulSPEED_Val_Old = ulCap_Val;


473+


472-
++         }


474+


473-
++      }


475+


474-
++


476+


475-
++   }


477+


476-
++


478+


477-
++   if(ulStatus & GPT_OF1){


479+


478-
++


480+


479-
++      evt->event_handler(evt);


481+


480-
++   }


482+


481-
++


483+


482-
++   if(__raw_readl(timer_base + MX3_TCMP) < __raw_readl(timer_base + MX3_TCN)) evt->event_handler(evt);


484+


483-
++


485+


484-
++   return IRQ_HANDLED;


486+


485-
+


487+


486-
+-	return IRQ_HANDLED;


488+


487-
+ }


489+


488-
+


490+


489-
++


491+


490-
++


492+


491-
++/******************************************************************************/


493+


492-
++/*!


494+


493-
++


495+


494-
++\fn            CC_adr


496+


495-
++


497+


496-
++\brief         CC-Adresse setzen


498+


497-
++


499+


498-
++\return        != 0 --> Fehler


500+


499-
++                  0 --> Erfolg


501+


500-
++


502+


501-
++\param         ucChannel_nr  Kanal Nr.


503+


502-
++               pulPWM_adr    Addresse


504+


503-
++


505+


504-
++\author        Marcel Gudert


506+


505-
++


507+


506-
++*******************************************************************************/


508+


507-
++int SPEED_read( u32 *ulSPEED_val )


509+


508-
++{


510+


509-
++   /*CC1*/


511+


510-
++


512+


511-
++   /* Wurden beide Werte ( Low und Highedge) aktualisiert? */


513+


512-
++   if(aulSPEED_Val1[SPEED_HIGH_EDGE] && aulSPEED_Val1[SPEED_LOW_EDGE]){


514+


513-
++      /* neuen Wert berechnen */


515+


514-
++      aulSPEED_Val = aulSPEED_Val1[SPEED_HIGH_EDGE] + aulSPEED_Val1[SPEED_LOW_EDGE];


516+


515-
++      /* die Capture Werte löschen */


517+


516-
++      aulSPEED_Val1[SPEED_HIGH_EDGE] = 0;


518+


517-
++      aulSPEED_Val1[SPEED_LOW_EDGE] = 0;


519+


518-
++


520+


519-
++      /* Flag rücksetzen */


521+


520-
++      aucSPEED_Stat = 0;


522+


521-
++   }


523+


522-
++


524+


523-
++	/* Werte übergeben */


525+


524-
++   *ulSPEED_val   = aulSPEED_Val / 113;


526+


525-
++


527+


526-
++   return 0;


528+


527-
++


529+


528-
++}  /* eofn: */


530+


529-
++


531+


530-
++EXPORT_SYMBOL(SPEED_read);


532+


531-
++


533+


532-
++/******************************************************************************/


534+


533-
++/*!


535+


534-
++\fn            SPEED_reset_status


536+


535-
++


537+


536-
++\brief         CC-Event Ruecksetzen


538+


537-
++


539+


538-
++\return        != 0 --> Fehler


540+


539-
++                  0 --> Erfolg


541+


540-
++\author        Marcel Gudert


542+


541-
++


543+


542-
++*******************************************************************************/


544+


543-
++int SPEED_reset_status(void)


545+


544-
++{


546+


545-
++


547+


546-
++


548+


547-
++   /* Flags setzen */


549+


548-
++   aucSPEED_Stat = 1;


550+


549-
++


551+


550-
++   return 0;


552+


551-
++


553+


552-
++} /* eofn: SPEED_Stopp */


554+


553-
++


555+


554-
++EXPORT_SYMBOL(SPEED_reset_status);


556+


555-
++


557+


556-
++


558+


557-
++


559+


558-
++/******************************************************************************/


560+


559-
++/*!


561+


560-
++


562+


561-
++\fn            SPEED_adr         SPEED_read();


563+


562-
++


564+


563-
++


565+


564-
++\brief         CC-Adresse setzen


566+


565-
++


567+


566-
++\return        != 0 --> Fehler


568+


567-
++                  0 --> Erfolg


569+


568-
++


570+


569-
++\param         ucChannel_nr  Kanal Nr.


571+


570-
++               pulPWM_adr    Addresse


572+


571-
++


573+


572-
++\author        Marcel Gudert


574+


573-
++


575+


574-
++*******************************************************************************/


576+


575-
++int SPEED_get_status(void)


577+


576-
++{


578+


577-
++   return (int)aucSPEED_Stat;


579+


578-
++


580+


579-
++


581+


580-
++}  /* eofn:  */


582+


581-
++


583+


582-
++EXPORT_SYMBOL(SPEED_get_status);


584+


583-
++


585+


584-
++


586+


585-
++


587+


586-
+ static struct irqaction mxc_timer_irq = {


588+


587-
+ 	.name		= "i.MX Timer Tick",


589+


588-
+ 	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,


590+


589-
+@@ -297,8 +513,8 @@


591+


590-
+ #endif


592+


591-
+ 	} else if (cpu_is_mx2()) {


593+


592-
+ #ifdef CONFIG_ARCH_MX2


594+


593-
+-		timer_base = IO_ADDRESS(GPT1_BASE_ADDR);


595+


594-
+-		irq = MXC_INT_GPT1;


596+


595-
++		timer_base = IO_ADDRESS(GPT3_BASE_ADDR);


597+


596-
++		irq = MXC_INT_GPT3;


598+


597-
+ #endif


599+


598-
+ 	} else if (cpu_is_mx3()) {


600+


599-
+ #ifdef CONFIG_ARCH_MX3


601+


600-
+@@ -318,7 +534,7 @@


602+


601-
+ 	__raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */


603+


602-
+


604+


603-
+ 	if (timer_is_v2())


605+


604-
+-		tctl_val = MX3_TCTL_CLK_PER | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN;


606+


605-
++		tctl_val = MX3_TCTL_CLK_PER | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN | (3<<16);


607+


606-
+ 	else


608+


607-
+ 		tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;


609+


608-
+


610+


609-
+


611+


610-
+


612+


611613








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