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Quantron oldsvn r2782 motorbrücke pmux diff
Posted by Anonymous on Wed 28th Nov 2018 15:41
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view followups (newest first): Quantron motorbrückenpatch oldsvn r2782 motorbrücke pmux diff by Anonymous

  1. Index: /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1283853740.patch
  2. ===================================================================
  3. --- /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1283853740.patch (Revision 2781)
  4. +++ /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1283853740.patch (Revision 2782)
  5. @@ -194,7 +194,7 @@
  6.  +#define LCDC_LSCR 0x00120300
  7.  +#define LCDC_LRMCR 0x00000000
  8.  +#define LCDC_LDCR 0x00020010
  9. -+#define LCDC_LPCCR 0x00a9037f
  10. ++#define LCDC_LPCCR 0x00a903ff
  11.  +#define LCDC_LPCR 0xFA008B80
  12.  +#define LCDC_LPCR_PCD 0x4
  13.  +
  14. Index: /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/kernel-2.6.31-1327402865.patch.md5
  15. ===================================================================
  16. --- /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/kernel-2.6.31-1327402865.patch.md5      (Revision 0)
  17. +++ /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/kernel-2.6.31-1327402865.patch.md5      (Revision 2782)
  18. @@ -0,0 +1 @@
  19. +2baf10b6bf67f4c0f2d3cca766b2e8e8  ./freescale/pkgs/kernel-2.6.31-1327402865.patch
  20. Index: /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1330436059.patch
  21. ===================================================================
  22. --- /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1330436059.patch (Revision 0)
  23. +++ /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1330436059.patch (Revision 2782)
  24. @@ -0,0 +1,57 @@
  25. +diff --exclude CVS --exclude .git -uNr u-boot-2009.08/board/freescale/quantron_a/quantron_a.c u-boot-2009.08.modified/board/freescale/quantron_a/quantron_a.c
  26. +--- u-boot-2009.08/board/freescale/quantron_a/quantron_a.c     2012-02-28 14:34:25.000000000 +0100
  27. ++++ u-boot-2009.08.modified/board/freescale/quantron_a/quantron_a.c    2012-02-28 14:26:18.000000000 +0100
  28. +@@ -168,6 +168,45 @@
  29. + int board_init(void)
  30. + {
  31. +       setup_soc_rev();
  32. ++
  33. ++         mxc_iomux_set_pad(MX25_PIN_PWM, PAD_CTL_PKE_ENABLE |
  34. ++              PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
  35. ++
  36. ++
  37. ++         mxc_iomux_set_pad(MX25_PIN_PWM, PAD_CTL_PKE_ENABLE |
  38. ++              PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
  39. ++
  40. ++         mxc_request_iomux(MX25_PIN_CSI_HSYNC, MUX_CONFIG_ALT5);
  41. ++         mxc_iomux_set_pad(MX25_PIN_CSI_HSYNC, PAD_CTL_PKE_ENABLE |
  42. ++                                PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
  43. ++       mxc_set_gpio_dataout(MX25_PIN_CSI_HSYNC, 0);
  44. ++
  45. ++         mxc_request_iomux(MX25_PIN_CSPI1_RDY, MUX_CONFIG_ALT5);
  46. ++         mxc_iomux_set_pad(MX25_PIN_CSPI1_RDY, PAD_CTL_PKE_ENABLE |
  47. ++                                PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
  48. ++       mxc_set_gpio_dataout(MX25_PIN_CSPI1_RDY, 0);
  49. ++
  50. ++         mxc_request_iomux(MX25_PIN_UART2_CTS, MUX_CONFIG_ALT5);
  51. ++         mxc_iomux_set_pad(MX25_PIN_UART2_CTS, PAD_CTL_PKE_ENABLE |
  52. ++                                PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
  53. ++       mxc_set_gpio_direction(MX25_PIN_UART2_CTS, 0);           /* Als Ausgang definieren */
  54. ++       mxc_set_gpio_dataout(MX25_PIN_UART2_CTS, 0);
  55. ++
  56. ++         mxc_request_iomux(MX25_PIN_CSI_MCLK, MUX_CONFIG_ALT5);
  57. ++         mxc_iomux_set_pad(MX25_PIN_CSI_MCLK, PAD_CTL_PKE_ENABLE |
  58. ++                                PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
  59. ++      mxc_set_gpio_dataout(MX25_PIN_CSI_MCLK, 0);
  60. ++
  61. ++         mxc_request_iomux(MX25_PIN_CSI_VSYNC, MUX_CONFIG_ALT5);
  62. ++         mxc_iomux_set_pad(MX25_PIN_CSI_VSYNC, PAD_CTL_PKE_ENABLE |
  63. ++                                PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
  64. ++      mxc_set_gpio_dataout(MX25_PIN_CSI_VSYNC, 0);
  65. ++
  66. ++         mxc_request_iomux(MX25_PIN_CSI_D8, MUX_CONFIG_ALT5);
  67. ++         mxc_iomux_set_pad(MX25_PIN_CSI_D8, PAD_CTL_PKE_ENABLE |
  68. ++                                PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
  69. ++      mxc_set_gpio_dataout(MX25_PIN_CSI_D8, 0);
  70. ++
  71. +       /* setup pins for UART5 */
  72. +       /* UART 5 IOMUX Configs */
  73. +          mxc_request_iomux(MX25_PIN_PWM, MUX_CONFIG_FUNC);
  74. +@@ -187,6 +226,7 @@
  75. +                         INPUT_CTL_PATH1);
  76. +
  77. +
  78. ++
  79. +       /* setup pins for FEC */
  80. +       mxc_request_iomux(MX25_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
  81. +       mxc_request_iomux(MX25_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
  82. Index: /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1283853740.patch.md5
  83. ===================================================================
  84. --- /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1283853740.patch.md5     (Revision 2781)
  85. +++ /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1283853740.patch.md5     (Revision 2782)
  86. @@ -1 +1 @@
  87. -24cb90163505e390889987c5f9a6d203  u-boot-2009.08-1283853740.patch
  88. +419a5f9f6301998ff199bf8c44f8aceb  ./freescale/pkgs/u-boot-2009.08-1283853740.patch
  89. Index: /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1330436059.patch.md5
  90. ===================================================================
  91. --- /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1330436059.patch.md5     (Revision 0)
  92. +++ /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1330436059.patch.md5     (Revision 2782)
  93. @@ -0,0 +1 @@
  94. +1b853c6f4860feecbf74398cf024163e  ./freescale/pkgs/u-boot-2009.08-1330436059.patch
  95. Index: /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/kernel-2.6.31-1327402865.patch
  96. ===================================================================
  97. --- /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/kernel-2.6.31-1327402865.patch  (Revision 0)
  98. +++ /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/kernel-2.6.31-1327402865.patch  (Revision 2782)
  99. @@ -0,0 +1,511 @@
  100. +diff --exclude CVS --exclude .git -uNr linux-2.6.31/arch/arm/mach-mx25/mx25_qa.c linux-2.6.31.modified/arch/arm/mach-mx25/mx25_qa.c
  101. +--- linux-2.6.31/arch/arm/mach-mx25/mx25_qa.c  2012-02-27 12:12:26.000000000 +0100
  102. ++++ linux-2.6.31.modified/arch/arm/mach-mx25/mx25_qa.c 2012-02-27 11:53:00.000000000 +0100
  103. +@@ -346,10 +346,14 @@
  104. +
  105. + static void __init mx25_qa_timer_init(void)
  106. + {
  107. ++   /* Clock source fuer den gpt ist ahb_div */
  108. ++   __raw_writel(__raw_readl(MXC_CCM_BASE+0x64) & ~(1 << 5),
  109. ++                MXC_CCM_BASE + 0x64);
  110. ++
  111. +       mx25_clocks_init(24000000);
  112. + }
  113. +
  114. +-static struct sys_timer mxc_timer = {
  115. ++static struct sys_timer mxc_timer = {
  116. +    .init      = mx25_qa_timer_init,
  117. + };
  118. +
  119. +diff --exclude CVS --exclude .git -uNr linux-2.6.31/drivers/mxc/adc/imx_adc.c linux-2.6.31.modified/drivers/mxc/adc/imx_adc.c
  120. +--- linux-2.6.31/drivers/mxc/adc/imx_adc.c     2012-01-24 12:01:56.000000000 +0100
  121. ++++ linux-2.6.31.modified/drivers/mxc/adc/imx_adc.c    2012-01-24 11:55:41.000000000 +0100
  122. +@@ -48,6 +48,17 @@
  123. + static int suspend_flag;
  124. +
  125. + /*!
  126. ++ * To indicate that the touchscreen was touched at least one time
  127. ++ */
  128. ++static bool touched = false;
  129. ++
  130. ++/*!
  131. ++ * The time in ms to wait between reading the ADCStatus Flag
  132. ++ * while the screen wasn't touched since last boot up
  133. ++ */
  134. ++#define ADC_STATUS_READING_GAP      300
  135. ++
  136. ++/*!
  137. +  * The suspendq is used by blocking application calls
  138. +  */
  139. + static wait_queue_head_t suspendq;
  140. +@@ -285,8 +296,17 @@
  141. +               __raw_writel(reg, tsc_base + TCQMR);
  142. +
  143. +               wait_event_interruptible(tsq, ts_data_ready);
  144. +-              while (!(__raw_readl(tsc_base + TCQSR) & CQSR_EOQ))
  145. ++
  146. ++              while (!(__raw_readl(tsc_base + TCQSR) & CQSR_EOQ)){
  147. ++
  148. ++                      // When the screen was not touched since bootup, wait a bit
  149. ++                      // otherwise this "while" would run full powered until the
  150. ++                      // screen is touched.
  151. ++                      if (!touched) {
  152. ++                      msleep(ADC_STATUS_READING_GAP);
  153. ++                      }
  154. +                       continue;
  155. ++              }
  156. +               /* stop the conversion */
  157. +               reg = __raw_readl(tsc_base + TCQCR);
  158. +               reg &= ~CQCR_QSM_MASK;
  159. +@@ -370,6 +390,10 @@
  160. +
  161. +       if (tsi_data == FQS_DATA)
  162. +               up(&ts_convert_mutex);
  163. ++
  164. ++      /* Now we know that the touchscreen was touched at least one time */
  165. ++      touched = true;
  166. ++
  167. +       return IMX_ADC_SUCCESS;
  168. + }
  169. +
  170. +diff --exclude CVS --exclude .git -uNr linux-2.6.31/drivers/video/mxc/mx2fb.c linux-2.6.31.modified/drivers/video/mxc/mx2fb.c
  171. +--- linux-2.6.31/drivers/video/mxc/mx2fb.c     2012-01-24 12:01:57.000000000 +0100
  172. ++++ linux-2.6.31.modified/drivers/video/mxc/mx2fb.c    2012-01-24 11:23:35.000000000 +0100
  173. +@@ -1086,7 +1086,7 @@
  174. + void mx2fb_set_brightness(uint8_t level)
  175. + {
  176. +       /* Set LCDC PWM contract control register */
  177. +-      __raw_writel(0x00A90300 | level, LCDC_REG(LCDC_LPCCR));
  178. ++      __raw_writel(0, LCDC_REG(LCDC_LPCCR));
  179. + }
  180. +
  181. + EXPORT_SYMBOL(mx2fb_set_brightness);
  182. +
  183. +diff --exclude CVS --exclude .git -uNr linux-2.6.31/arch/arm/mach-mx25/clock.c linux-2.6.31.modified/arch/arm/mach-mx25/clock.c
  184. +--- linux-2.6.31/arch/arm/mach-mx25/clock.c    2011-04-12 11:03:01.000000000 +0200
  185. ++++ linux-2.6.31.modified/arch/arm/mach-mx25/clock.c   2011-04-05 11:48:32.000000000 +0200
  186. +@@ -1746,6 +1746,6 @@
  187. +    clk_enable(&gpt3_clk[1]);
  188. +    clk_enable(&gpt4_clk[1]);
  189. +
  190. +-      mxc_timer_init(&gpt1_clk[0], IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1);
  191. ++      mxc_timer_init(&gpt1_clk[0], IO_ADDRESS(GPT3_BASE_ADDR), MXC_INT_GPT3);
  192. +       return 0;
  193. + }
  194. +diff --exclude CVS --exclude .git -uNr linux-2.6.31/arch/arm/mach-mx25/devices.c linux-2.6.31.modified/arch/arm/mach-mx25/devices.c
  195. +--- linux-2.6.31/arch/arm/mach-mx25/devices.c  2011-04-12 11:03:02.000000000 +0200
  196. ++++ linux-2.6.31.modified/arch/arm/mach-mx25/devices.c 2011-04-05 11:27:36.000000000 +0200
  197. +@@ -560,15 +560,21 @@
  198. +             .flags = IORESOURCE_MEM,
  199. +       },
  200. +
  201. +-      [2] = {
  202. +-            .start = GPT3_BASE_ADDR,
  203. +-            .end = GPT3_BASE_ADDR + SZ_4K - 1,
  204. +-            .flags = IORESOURCE_MEM,
  205. ++   [2] = {
  206. ++         .start = GPT1_BASE_ADDR,
  207. ++         .end = GPT1_BASE_ADDR + SZ_4K - 1,
  208. ++         .flags = IORESOURCE_MEM,
  209. +    },
  210. +
  211. +       [3] = {
  212. ++            .start = GPT2_BASE_ADDR,
  213. ++            .end = GPT2_BASE_ADDR + SZ_4K - 1,
  214. ++            .flags = IORESOURCE_MEM,
  215. ++   },
  216. ++
  217. ++      [4] = {
  218. +             .start = GPT4_BASE_ADDR,
  219. +-            .end = GPT4_BASE_ADDR + SZ_4K - 1,
  220. ++            .end = GPT4_BASE_ADDR + SZ_4K - 1,  
  221. +             .flags = IORESOURCE_MEM,
  222. +       },
  223. +    
  224. +                                                                          
  225. +
  226. +
  227. +
  228. +diff --exclude CVS --exclude .git -uNr linux-2.6.31/arch/arm/mach-mx25/mx25_qa_gpio.c linux-2.6.31.modified/arch/arm/mach-mx25/mx25_qa_gpio.c
  229. +--- linux-2.6.31/arch/arm/mach-mx25/mx25_qa_gpio.c     2011-04-12 11:03:02.000000000 +0200
  230. ++++ linux-2.6.31.modified/arch/arm/mach-mx25/mx25_qa_gpio.c    2011-04-05 09:18:26.000000000 +0200
  231. +@@ -358,40 +358,41 @@
  232. + }
  233. + EXPORT_SYMBOL(gpio_pwm_inactive);
  234. +
  235. +-void gpio_cc_active(int cc_nr){
  236. ++void gpio_cc_active(void){
  237. +    /*
  238. +     * Configure the IOMUX control registers for the compare capture signals
  239. +     */
  240. +-   switch ( cc_nr ) {
  241. +-      case 0:
  242. +-         /* CC3 IOMUX Configs */
  243. +-         mxc_request_iomux(MX25_PIN_UART1_RTS, MUX_CONFIG_ALT2);
  244. +-         mxc_iomux_set_pad(MX25_PIN_UART1_RTS, PAD_CTL_47K_PU);
  245. +-         break;
  246. +-      case 1:
  247. +-         /* CC4 IOMUX Configs */
  248. +-         mxc_request_iomux(MX25_PIN_CONTRAST, MUX_CONFIG_ALT1);
  249. +-         mxc_iomux_set_pad(MX25_PIN_CONTRAST, PAD_CTL_47K_PU);
  250. +-         break;
  251. +-      default:
  252. +-         break;
  253. +-   }
  254. ++   /* CC3 IOMUX Configs */
  255. ++   mxc_request_iomux(MX25_PIN_UART1_RTS, MUX_CONFIG_ALT2);
  256. ++   mxc_iomux_set_pad(MX25_PIN_UART1_RTS, PAD_CTL_47K_PU);
  257. ++  
  258. ++   mxc_request_iomux(MX25_PIN_CONTRAST, MUX_CONFIG_ALT1);
  259. ++   mxc_iomux_set_pad(MX25_PIN_CONTRAST, PAD_CTL_47K_PU);
  260. ++
  261. ++   mxc_request_iomux(MX25_PIN_GPIO_C, MUX_CONFIG_ALT4);
  262. ++   mxc_iomux_set_pad(MX25_PIN_GPIO_C, PAD_CTL_47K_PU);
  263. ++
  264. ++   mxc_request_iomux(MX25_PIN_UART2_RTS, MUX_CONFIG_ALT3);
  265. ++   mxc_iomux_set_pad(MX25_PIN_UART2_RTS, PAD_CTL_47K_PU);
  266. ++
  267. + }
  268. + EXPORT_SYMBOL(gpio_cc_active);
  269. +
  270. +-void gpio_cc_inactive(int cc_nr){
  271. +-   switch ( cc_nr ) {
  272. +-      case 0:
  273. +-         gpio_request(IOMUX_TO_GPIO(MX25_PIN_UART1_RTS), NULL);
  274. +-         mxc_free_iomux(MX25_PIN_UART1_RTS, MUX_CONFIG_GPIO);
  275. +-         break;
  276. +-      case 1:
  277. +-         mxc_free_iomux(MX25_PIN_CONTRAST, MUX_CONFIG_FUNC);
  278. +-         break;        
  279. +
  280. +-      default:
  281. +-         break;
  282. +-   }
  283. ++void gpio_cc_inactive(void){
  284. ++
  285. ++   gpio_request(IOMUX_TO_GPIO(MX25_PIN_UART1_RTS), NULL);
  286. ++   mxc_free_iomux(MX25_PIN_UART1_RTS, MUX_CONFIG_GPIO);
  287. ++
  288. ++   mxc_free_iomux(MX25_PIN_CONTRAST, MUX_CONFIG_FUNC);
  289. ++
  290. ++   gpio_request(IOMUX_TO_GPIO(MX25_PIN_GPIO_C), NULL);
  291. ++   mxc_free_iomux(MX25_PIN_GPIO_C, MUX_CONFIG_GPIO);
  292. ++
  293. ++   gpio_request(IOMUX_TO_GPIO(MX25_PIN_UART2_RTS), NULL);
  294. ++   mxc_free_iomux(MX25_PIN_UART2_RTS, MUX_CONFIG_GPIO);
  295. ++
  296. ++
  297. + }
  298. + EXPORT_SYMBOL(gpio_cc_inactive);
  299. +
  300. +diff --exclude CVS --exclude .git -uNr linux-2.6.31/arch/arm/plat-mxc/include/mach/mxc_timer.h linux-2.6.31.modified/arch/arm/plat-mxc/include/mach/mxc_timer.h
  301. +--- linux-2.6.31/arch/arm/plat-mxc/include/mach/mxc_timer.h    2011-04-12 11:02:52.000000000 +0200
  302. ++++ linux-2.6.31.modified/arch/arm/plat-mxc/include/mach/mxc_timer.h   2011-04-05 11:39:36.000000000 +0200
  303. +@@ -67,8 +67,8 @@
  304. + }
  305. +
  306. + #elif defined(CONFIG_ARCH_MX2)
  307. +-#define TIMER_BASE            IO_ADDRESS(GPT1_BASE_ADDR)
  308. +-#define TIMER_INTERRUPT               MXC_INT_GPT1
  309. ++#define TIMER_BASE            IO_ADDRESS(GPT3_BASE_ADDR)
  310. ++#define TIMER_INTERRUPT               MXC_INT_GPT3
  311. +
  312. + #define MXC_TCTL   0x00
  313. + #define TCTL_VAL              TCTL_CLK_PCLK1
  314. +diff --exclude CVS --exclude .git -uNr linux-2.6.31/arch/arm/plat-mxc/time.c linux-2.6.31.modified/arch/arm/plat-mxc/time.c
  315. +--- linux-2.6.31/arch/arm/plat-mxc/time.c      2011-04-12 11:02:52.000000000 +0200
  316. ++++ linux-2.6.31.modified/arch/arm/plat-mxc/time.c     2011-04-05 11:37:00.000000000 +0200
  317. +@@ -59,6 +59,83 @@
  318. + #define MX3_TCMP              0x10
  319. +
  320. + #define timer_is_v2() (!(cpu_is_mx1() || cpu_is_mx2()) || cpu_is_mx25())
  321. ++/* Anzahl der CC-Kanaele */
  322. ++#define SPEED_CHANNELS                        ((uchar)  2 )
  323. ++
  324. ++
  325. ++#define SPEED_DEF_PRESC                       ((ushort) 664   )
  326. ++
  327. ++/* CC vituelle Adressen Register */
  328. ++#define GPTCR(x)                      (((ulong *) x)+0 )
  329. ++#define GPTPR(x)                      (((ulong *) x)+1 )
  330. ++#define GPTSR(x)                      (((ulong *) x)+2 )
  331. ++#define GPTIR(x)                      (((ulong *) x)+3 )
  332. ++#define GPTICR1(x)                    (((ulong *) x)+7 )
  333. ++#define GPTICR2(x)                    (((ulong *) x)+8 )
  334. ++#define GPTCNT(x)                     (((ulong *) x)+9 )
  335. ++
  336. ++
  337. ++/// PWM Bits
  338. ++#define GPT_IM2(x)                          ((ulong) ((uchar)x<<18))
  339. ++#define GPT_IM1(x)                       ((ulong) ((uchar)x<<16))
  340. ++#define GPT_SWR                       ((ulong) 1<<15)
  341. ++#define GPT_FRR                       ((ulong) 1<<9)
  342. ++#define GPT_CLKSRC(x)                       ((ulong) ((uchar)x<<6))
  343. ++#define GPT_STOPEN                    ((ulong) 1<<5)      
  344. ++#define GPT_WAITEN                    ((ulong) 1<<3)
  345. ++#define GPT_ENMOD                        ((ulong) 1<<1)
  346. ++#define GPT_EN                              ((ulong) 1<<0)
  347. ++                                              
  348. ++#define GPT_ROVIE                   ((ulong) 1<<5)
  349. ++#define GPT_IF2IE                        ((ulong) 1<<4)
  350. ++#define GPT_IF1IE                           ((ulong) 1<<3)
  351. ++
  352. ++#define GPT_ROV                             ((ulong) 1<<5)
  353. ++#define GPT_IF2                          ((ulong) 1<<4)
  354. ++#define GPT_IF1                             ((ulong) 1<<3)
  355. ++#define GPT_OF1                             ((ulong) 1<<0)
  356. ++
  357. ++#define GPT_CLKSRC_OFF                ((ulong) 0<<6)
  358. ++#define GPT_CLKSRC_IPG                ((ulong) 1<<6)
  359. ++#define GPT_CLKSRC_IPG_HF             ((ulong) 2<<6)
  360. ++#define GPT_CLKSRC_IND_CLKIN          ((ulong) 3<<6)
  361. ++#define GPT_CLKSRC_IPG_32K            ((ulong) 4<<6)
  362. ++
  363. ++#define SPEED_NO_EVENT                                   0
  364. ++
  365. ++
  366. ++#define SPEED                                         0
  367. ++
  368. ++
  369. ++#define SPEED_HIGH_EDGE                        0
  370. ++#define SPEED_LOW_EDGE                         1
  371. ++
  372. ++/*******************************************************************************
  373. ++@Typdefinitionen (modullokal)
  374. ++*******************************************************************************/
  375. ++
  376. ++/*******************************************************************************
  377. ++@Variablen (modullokal)
  378. ++*******************************************************************************/
  379. ++
  380. ++
  381. ++/* Virtuelle Adresse fuer die PWM Resourcen */
  382. ++volatile static ulong *paulSPEED_virtualbase;
  383. ++
  384. ++/* Capture Values 1 */
  385. ++volatile static u32 aulSPEED_Val;
  386. ++
  387. ++/* Capture Values Channel 1 */
  388. ++volatile static u32 aulSPEED_Val1[2];
  389. ++
  390. ++/* old Capture Values */
  391. ++volatile static u32 aulSPEED_Val_Old;
  392. ++
  393. ++/* Capture Status */
  394. ++volatile static u8 aucSPEED_Stat;
  395. ++
  396. ++/* Toggle Bit */
  397. ++volatile static u8 aucSPEED_Toggle;
  398. +
  399. + static struct clock_event_device clockevent_mxc;
  400. + static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
  401. +@@ -79,8 +156,10 @@
  402. +
  403. + static inline void gpt_irq_enable(void)
  404. + {
  405. +-      if (timer_is_v2())
  406. +-              __raw_writel(1<<0, timer_base + MX3_IR);
  407. ++      if (timer_is_v2()) {
  408. ++              __raw_writel(0x09, timer_base + MX3_IR);
  409. ++       printk("mxc_set_mo\n\n\n\n\n\n");                          
  410. ++   }
  411. +       else {
  412. +               __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
  413. +                       timer_base + MXC_TCTL);
  414. +@@ -94,7 +173,7 @@
  415. +       if (cpu_is_mx2())
  416. +               __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, timer_base + MX1_2_TSTAT);
  417. +       if (timer_is_v2())
  418. +-              __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT);
  419. ++              __raw_writel(0x09, timer_base + MX3_TSTAT);
  420. + }
  421. +
  422. + static cycle_t mx1_2_get_cycles(struct clocksource *cs)
  423. +@@ -234,20 +313,157 @@
  424. + static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
  425. + {
  426. +       struct clock_event_device *evt = &clockevent_mxc;
  427. +-      uint32_t tstat;
  428. ++   ulong ulCap_Val=0;
  429. ++   ulong ulStatus;
  430. +
  431. +-      if (timer_is_v2())
  432. +-              tstat = __raw_readl(timer_base + MX3_TSTAT);
  433. +-      else
  434. +-              tstat = __raw_readl(timer_base + MX1_2_TSTAT);
  435. ++   ulStatus = __raw_readl(timer_base + MX3_TSTAT);
  436. ++   gpt_irq_acknowledge();
  437. ++
  438. ++
  439. ++   if(ulStatus & GPT_IF1){
  440. ++      ulCap_Val =  __raw_readl(timer_base + 0x1C);
  441. ++      
  442. ++
  443. ++      /* Wenn ein Timerueberlauf stattgefunden hat */
  444. ++      if( (ulStatus & GPT_IF1)  && (ulCap_Val < aulSPEED_Val_Old) ){
  445. ++
  446. ++         /* Capture-Werte < 10 werden nicht beruecksichtigt */
  447. ++         if( ( (0xFFFFFFFF - aulSPEED_Val_Old) + ulCap_Val) > 10){
  448. ++            /* abwechselnd Werte fuer High und Lowedge schreiben */
  449. ++            aucSPEED_Toggle = (aucSPEED_Toggle+1)&0x01;
  450. ++            aulSPEED_Val1[aucSPEED_Toggle] = (0xFFFFFFFF - aulSPEED_Val_Old) + ulCap_Val;
  451. ++
  452. ++            /* den alten Capturewert behalten*/
  453. ++            aulSPEED_Val_Old = ulCap_Val;
  454. ++         }
  455. ++
  456. ++      }
  457. ++
  458. ++      /* Wenn kein Timerueberlauf stattgefunden hat */
  459. ++      if( (ulStatus & GPT_IF1) &&(ulCap_Val > aulSPEED_Val_Old) ){
  460. ++
  461. ++         /* Capture-Werte < 10 werden nicht beruecksichtigt */
  462. ++         if( (ulCap_Val - aulSPEED_Val_Old) > 10){
  463. +
  464. +-      gpt_irq_acknowledge();
  465. ++            /* abwechselnd Werte fuer High und Lowedge schreiben */
  466. ++            aucSPEED_Toggle = (aucSPEED_Toggle+1)&0x01;
  467. ++            aulSPEED_Val1[aucSPEED_Toggle] = ulCap_Val - aulSPEED_Val_Old;
  468. +
  469. +-      evt->event_handler(evt);
  470. ++            /* den alten Capturewert behalten*/
  471. ++            aulSPEED_Val_Old = ulCap_Val;
  472. ++         }
  473. ++      }
  474. ++
  475. ++   }    
  476. ++
  477. ++   if(ulStatus & GPT_OF1){
  478. ++
  479. ++      evt->event_handler(evt);
  480. ++   }
  481. ++
  482. ++   if(__raw_readl(timer_base + MX3_TCMP) < __raw_readl(timer_base + MX3_TCN)) evt->event_handler(evt);
  483. ++
  484. ++   return IRQ_HANDLED;
  485. +
  486. +-      return IRQ_HANDLED;
  487. + }
  488. +
  489. ++  
  490. ++
  491. ++/******************************************************************************/
  492. ++/*!
  493. ++
  494. ++\fn            CC_adr
  495. ++
  496. ++\brief         CC-Adresse setzen
  497. ++
  498. ++\return        != 0 --> Fehler
  499. ++                  0 --> Erfolg
  500. ++
  501. ++\param         ucChannel_nr  Kanal Nr.
  502. ++               pulPWM_adr    Addresse
  503. ++
  504. ++\author        Marcel Gudert
  505. ++
  506. ++*******************************************************************************/
  507. ++int SPEED_read( u32 *ulSPEED_val )
  508. ++{
  509. ++   /*CC1*/
  510. ++
  511. ++   /* Wurden beide Werte ( Low und Highedge) aktualisiert? */
  512. ++   if(aulSPEED_Val1[SPEED_HIGH_EDGE] && aulSPEED_Val1[SPEED_LOW_EDGE]){
  513. ++      /* neuen Wert berechnen */
  514. ++      aulSPEED_Val = aulSPEED_Val1[SPEED_HIGH_EDGE] + aulSPEED_Val1[SPEED_LOW_EDGE];
  515. ++      /* die Capture Werte löschen */
  516. ++      aulSPEED_Val1[SPEED_HIGH_EDGE] = 0;
  517. ++      aulSPEED_Val1[SPEED_LOW_EDGE] = 0;
  518. ++
  519. ++      /* Flag rücksetzen */
  520. ++      aucSPEED_Stat = 0;
  521. ++   }
  522. ++
  523. ++      /* Werte übergeben */
  524. ++   *ulSPEED_val   = aulSPEED_Val / 113;
  525. ++                  
  526. ++   return 0;
  527. ++
  528. ++}  /* eofn: */
  529. ++
  530. ++EXPORT_SYMBOL(SPEED_read);
  531. ++
  532. ++/******************************************************************************/
  533. ++/*!
  534. ++\fn            SPEED_reset_status
  535. ++
  536. ++\brief         CC-Event Ruecksetzen
  537. ++
  538. ++\return        != 0 --> Fehler
  539. ++                  0 --> Erfolg
  540. ++\author        Marcel Gudert
  541. ++
  542. ++*******************************************************************************/
  543. ++int SPEED_reset_status(void)
  544. ++{
  545. ++
  546. ++
  547. ++   /* Flags setzen */
  548. ++   aucSPEED_Stat = 1;
  549. ++
  550. ++   return 0;
  551. ++
  552. ++} /* eofn: SPEED_Stopp */
  553. ++
  554. ++EXPORT_SYMBOL(SPEED_reset_status);
  555. ++
  556. ++
  557. ++
  558. ++/******************************************************************************/
  559. ++/*!
  560. ++
  561. ++\fn            SPEED_adr         SPEED_read();
  562. ++
  563. ++
  564. ++\brief         CC-Adresse setzen
  565. ++
  566. ++\return        != 0 --> Fehler
  567. ++                  0 --> Erfolg
  568. ++
  569. ++\param         ucChannel_nr  Kanal Nr.
  570. ++               pulPWM_adr    Addresse
  571. ++
  572. ++\author        Marcel Gudert
  573. ++
  574. ++*******************************************************************************/
  575. ++int SPEED_get_status(void)
  576. ++{
  577. ++   return (int)aucSPEED_Stat;
  578. ++
  579. ++
  580. ++}  /* eofn:  */
  581. ++
  582. ++EXPORT_SYMBOL(SPEED_get_status);
  583. ++
  584. ++
  585. ++
  586. + static struct irqaction mxc_timer_irq = {
  587. +       .name           = "i.MX Timer Tick",
  588. +       .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
  589. +@@ -297,8 +513,8 @@
  590. + #endif
  591. +       } else if (cpu_is_mx2()) {
  592. + #ifdef CONFIG_ARCH_MX2
  593. +-              timer_base = IO_ADDRESS(GPT1_BASE_ADDR);
  594. +-              irq = MXC_INT_GPT1;
  595. ++              timer_base = IO_ADDRESS(GPT3_BASE_ADDR);
  596. ++              irq = MXC_INT_GPT3;
  597. + #endif
  598. +       } else if (cpu_is_mx3()) {
  599. + #ifdef CONFIG_ARCH_MX3
  600. +@@ -318,7 +534,7 @@
  601. +       __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
  602. +
  603. +       if (timer_is_v2())
  604. +-              tctl_val = MX3_TCTL_CLK_PER | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN;
  605. ++              tctl_val = MX3_TCTL_CLK_PER | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN | (3<<16);
  606. +       else
  607. +               tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
  608. +
  609. +
  610. +

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