Index: /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1330436059.patch
===================================================================
--- /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1330436059.patch (Revision 0)
+++ /home/rmainz/tmp/svneckelmanngroup_search/max/quantron_a/trunk/src/ltib_custom/pkgs/u-boot-2009.08-1330436059.patch (Revision 2782)
@@ -0,0 +1,57 @@
+diff --exclude CVS --exclude .git -uNr u-boot-2009.08/board/freescale/quantron_a/quantron_a.c u-boot-2009.08.modified/board/freescale/quantron_a/quantron_a.c
+--- u-boot-2009.08/board/freescale/quantron_a/quantron_a.c     2012-02-28 14:34:25.000000000 +0100
++++ u-boot-2009.08.modified/board/freescale/quantron_a/quantron_a.c    2012-02-28 14:26:18.000000000 +0100
+@@ -168,6 +168,45 @@
+ int board_init(void)
+ {
+       setup_soc_rev();
++
++         mxc_iomux_set_pad(MX25_PIN_PWM, PAD_CTL_PKE_ENABLE |
++              PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
++
++
++         mxc_iomux_set_pad(MX25_PIN_PWM, PAD_CTL_PKE_ENABLE |
++              PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
++
++         mxc_request_iomux(MX25_PIN_CSI_HSYNC, MUX_CONFIG_ALT5);
++         mxc_iomux_set_pad(MX25_PIN_CSI_HSYNC, PAD_CTL_PKE_ENABLE |
++                                PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
++       mxc_set_gpio_dataout(MX25_PIN_CSI_HSYNC, 0);
++
++         mxc_request_iomux(MX25_PIN_CSPI1_RDY, MUX_CONFIG_ALT5);
++         mxc_iomux_set_pad(MX25_PIN_CSPI1_RDY, PAD_CTL_PKE_ENABLE |
++                                PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
++       mxc_set_gpio_dataout(MX25_PIN_CSPI1_RDY, 0);
++
++         mxc_request_iomux(MX25_PIN_UART2_CTS, MUX_CONFIG_ALT5);
++         mxc_iomux_set_pad(MX25_PIN_UART2_CTS, PAD_CTL_PKE_ENABLE |
++                                PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
++       mxc_set_gpio_direction(MX25_PIN_UART2_CTS, 0);           /* Als Ausgang definieren */
++       mxc_set_gpio_dataout(MX25_PIN_UART2_CTS, 0);
++
++         mxc_request_iomux(MX25_PIN_CSI_MCLK, MUX_CONFIG_ALT5);
++         mxc_iomux_set_pad(MX25_PIN_CSI_MCLK, PAD_CTL_PKE_ENABLE |
++                                PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
++      mxc_set_gpio_dataout(MX25_PIN_CSI_MCLK, 0);
++
++         mxc_request_iomux(MX25_PIN_CSI_VSYNC, MUX_CONFIG_ALT5);
++         mxc_iomux_set_pad(MX25_PIN_CSI_VSYNC, PAD_CTL_PKE_ENABLE |
++                                PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
++      mxc_set_gpio_dataout(MX25_PIN_CSI_VSYNC, 0);
++
++         mxc_request_iomux(MX25_PIN_CSI_D8, MUX_CONFIG_ALT5);
++         mxc_iomux_set_pad(MX25_PIN_CSI_D8, PAD_CTL_PKE_ENABLE |
++                                PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
++      mxc_set_gpio_dataout(MX25_PIN_CSI_D8, 0);