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Quantron valgrind patch
Posted by Anonymous on Tue 29th Oct 2019 12:08
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  1. From d7945b936d387d1b7645dc6d4666b45990bc8557 Mon Sep 17 00:00:00 2001
  2. From: Roland Mainz <r.mainz@eckelmann.de>
  3. Date: Tue, 29 Oct 2019 10:35:29 +0100
  4. Subject: [PATCH 1/2] Enable valgrind and add valgrind support for armv5tejl
  5.  
  6. Enable building valgrind V3.14.0 and add support for Quantrons
  7. armv5tejl processor.
  8.  
  9. Thanks go to Chris Paulson-Ellis <chris@edesix.com> for helping a lot.
  10. ---
  11.  ptxdist/configs/ecu01/ptxconfig                    |   5 +-
  12.  .../0001-valgrind3140-armv5tejl-support.patch      | 897 +++++++++++++++++++++
  13.  ptxdist/patches/valgrind-3.14.0/autogen.sh         |  21 +
  14.  ptxdist/patches/valgrind-3.14.0/series             |   1 +
  15.  ptxdist/rules/valgrind.in                          |  16 +
  16.  ptxdist/rules/valgrind.make                        |  94 +++
  17.  6 files changed, 1031 insertions(+), 3 deletions(-)
  18.  create mode 100644 ptxdist/patches/valgrind-3.14.0/0001-valgrind3140-armv5tejl-support.patch
  19.  create mode 100755 ptxdist/patches/valgrind-3.14.0/autogen.sh
  20.  create mode 100644 ptxdist/patches/valgrind-3.14.0/series
  21.  create mode 100644 ptxdist/rules/valgrind.in
  22.  create mode 100644 ptxdist/rules/valgrind.make
  23.  
  24. diff --git a/ptxdist/configs/ecu01/ptxconfig b/ptxdist/configs/ecu01/ptxconfig
  25. index aa44107..a725eb0 100644
  26. --- a/ptxdist/configs/ecu01/ptxconfig
  27. +++ b/ptxdist/configs/ecu01/ptxconfig
  28. @@ -33,7 +33,6 @@ PTXCONF_PROJECT_BUILD_DEVEL=y
  29.  PTXCONF_PROJECT_CREATE_DEVPKGS=y
  30.  PTXCONF_PROJECT_USE_DEVPKGS=y
  31.  PTXCONF_PROJECT_DEVPKGDIR="/opt/OSELAS.BSP/${PTXCONF_PROJECT_VENDOR}/OSELAS.BSP-${PTXCONF_PROJECT_VENDOR}-${PTXCONF_PROJECT}${PTXCONF_PROJECT_VERSION}"
  32. -PTXCONF_PROJECT_DEVMIRROR=""
  33.  PTXCONF_RUNTIME=y
  34.  PTXCONF_BUILDTIME=y
  35.  PTXCONF_CONFIGFILE_VERSION="2012.10.0"
  36. @@ -66,7 +65,7 @@ PTXCONF_HOST_AUTOTOOLS_AUTOCONF=y
  37.  PTXCONF_HOST_AUTOTOOLS_AUTOMAKE=y
  38.  PTXCONF_HOST_AUTOTOOLS_LIBTOOL=y
  39.  # PTXCONF_HOST_CDRKIT is not set
  40. -# PTXCONF_HOST_CHRPATH is not set
  41. +PTXCONF_HOST_CHRPATH=y
  42.  # PTXCONF_HOST_CKERMIT is not set
  43.  # PTXCONF_HOST_CMAKE is not set
  44.  # PTXCONF_HOST_CRAMFS is not set
  45. @@ -200,7 +199,7 @@ PTXCONF_STRACE=y
  46.  PTXCONF_STRACE_SHARED=y
  47.  # PTXCONF_SYSSTAT is not set
  48.  PTXCONF_TRACE_CMD=y
  49. -# PTXCONF_VALGRIND is not set
  50. +PTXCONF_VALGRIND=y
  51.  
  52.  #
  53.  # ------------------------------------
  54. diff --git a/ptxdist/patches/valgrind-3.14.0/0001-valgrind3140-armv5tejl-support.patch b/ptxdist/patches/valgrind-3.14.0/0001-valgrind3140-armv5tejl-support.patch
  55. new file mode 100644
  56. index 0000000..b13ed5d
  57. --- /dev/null
  58. +++ b/ptxdist/patches/valgrind-3.14.0/0001-valgrind3140-armv5tejl-support.patch
  59. @@ -0,0 +1,897 @@
  60. +diff -Naur valgrind-3.14.0/configure.ac valgrind-3.14.0-armv5/configure.ac
  61. +--- valgrind-3.14.0/configure.ac       2018-10-09 08:26:33.000000000 +0100
  62. ++++ valgrind-3.14.0-armv5/configure.ac 2019-01-04 17:58:37.415112119 +0000
  63. +@@ -255,8 +255,15 @@
  64. +      armv7*)
  65. +       AC_MSG_RESULT([ok (${host_cpu})])
  66. +       ARCH_MAX="arm"
  67. ++      FLAG_MCPU_CORTEX_A8="-mcpu=cortex-a8"
  68. +       ;;
  69. +
  70. ++     arm*)
  71. ++       AC_MSG_RESULT([ok (${host_cpu})])
  72. ++       ARCH_MAX="arm"
  73. ++       FLAG_MCPU_CORTEX_A8=""
  74. ++       ;;
  75. ++
  76. +      aarch64*)
  77. +        AC_MSG_RESULT([ok (${host_cpu})])
  78. +        ARCH_MAX="arm64"
  79. +@@ -293,6 +300,8 @@
  80. +       ;;
  81. + esac
  82. +
  83. ++AC_SUBST(FLAG_MCPU_CORTEX_A8)
  84. ++
  85. + #----------------------------------------------------------------------------
  86. +
  87. + # Sometimes it's convenient to subvert the bi-arch build system and
  88. +diff -Naur valgrind-3.14.0/coregrind/m_dispatch/dispatch-arm-linux.S valgrind-3.14.0-armv5/coregrind/m_dispatch/dispatch-arm-linux.S
  89. +--- valgrind-3.14.0/coregrind/m_dispatch/dispatch-arm-linux.S  2018-05-05 08:42:22.000000000 +0100
  90. ++++ valgrind-3.14.0-armv5/coregrind/m_dispatch/dispatch-arm-linux.S    2019-01-04 17:58:37.416112114 +0000
  91. +@@ -67,10 +67,16 @@
  92. +            order to keep the stack 8-aligned. */
  93. +       push {r0, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr}
  94. +
  95. ++        ldr r4, =VG_(machine_arm_has_fpscr)
  96. ++        ldr r4, [r4]
  97. ++        cmp r4, #0
  98. ++        beq no_fpscr_setup
  99. ++
  100. +         /* set FPSCR to vex-required default value */
  101. +         mov  r4, #0
  102. +         fmxr fpscr, r4
  103. +
  104. ++no_fpscr_setup:
  105. +               /* Set up the guest state pointer */
  106. +         mov r8, r1
  107. +
  108. +@@ -87,6 +93,11 @@
  109. + /*----------------------------------------------------*/
  110. +
  111. + postamble:
  112. ++        ldr r4, =VG_(machine_arm_has_fpscr)
  113. ++        ldr r4, [r4]
  114. ++        cmp r4, #0
  115. ++        beq remove_frame
  116. ++
  117. +         /* At this point, r1 and r2 contain two
  118. +            words to be returned to the caller.  r1
  119. +            holds a TRC value, and r2 optionally may
  120. +@@ -101,8 +112,8 @@
  121. +         cmp  r4, #0
  122. +         beq  remove_frame /* we're OK */
  123. +         /* otherwise we have an invariant violation */
  124. +-        movw r1, #VG_TRC_INVARIANT_FAILED
  125. +-        movw r2, #0
  126. ++        mov  r1, #VG_TRC_INVARIANT_FAILED
  127. ++        mov  r2, #0
  128. +         /* fall through */
  129. +
  130. + remove_frame:
  131. +@@ -126,10 +137,19 @@
  132. +            handing the caller the pair (Chain_me_S, RA) */
  133. +         mov  r1, #VG_TRC_CHAIN_ME_TO_SLOW_EP
  134. +         mov  r2, lr
  135. ++#ifdef __ARM_ARCH_7A__
  136. +         /* 4 = movw r12, lo16(disp_cp_chain_me_to_slowEP)
  137. +            4 = movt r12, hi16(disp_cp_chain_me_to_slowEP)
  138. +            4 = blx  r12 */
  139. +         sub  r2, r2, #4+4+4
  140. ++#else
  141. ++        /* 4 = mov r12, #lo8(disp_cp_chain_me_to_slowEP)
  142. ++           4 = orr r12, r12, #lh8(disp_cp_chain_me_to_slowEP)
  143. ++           4 = orr r12, r12, #hl8(disp_cp_chain_me_to_slowEP)
  144. ++           4 = orr r12, r12, #hi8(disp_cp_chain_me_to_slowEP)
  145. ++           4 = blx  r12 */
  146. ++        sub  r2, r2, #4+4+4+4+4
  147. ++#endif
  148. +         b    postamble
  149. +
  150. + /* ------ Chain me to fast entry point ------ */
  151. +@@ -141,10 +161,19 @@
  152. +            handing the caller the pair (Chain_me_F, RA) */
  153. +         mov  r1, #VG_TRC_CHAIN_ME_TO_FAST_EP
  154. +         mov  r2, lr
  155. ++#ifdef __ARM_ARCH_7A__
  156. +         /* 4 = movw r12, lo16(disp_cp_chain_me_to_fastEP)
  157. +            4 = movt r12, hi16(disp_cp_chain_me_to_fastEP)
  158. +            4 = blx  r12 */
  159. +         sub  r2, r2, #4+4+4
  160. ++#else
  161. ++        /* 4 = mov r12, #lo8(disp_cp_chain_me_to_fastEP)
  162. ++           4 = orr r12, r12, #lh8(disp_cp_chain_me_to_fastEP)
  163. ++           4 = orr r12, r12, #hl8(disp_cp_chain_me_to_fastEP)
  164. ++           4 = orr r12, r12, #hi8(disp_cp_chain_me_to_fastEP)
  165. ++           4 = blx  r12 */
  166. ++        sub  r2, r2, #4+4+4+4+4
  167. ++#endif
  168. +         b    postamble
  169. +
  170. + /* ------ Indirect but boring jump ------ */
  171. +@@ -154,23 +183,40 @@
  172. +         ldr  r0, [r8, #OFFSET_arm_R15T]
  173. +
  174. +         /* stats only */
  175. ++#ifdef __ARM_ARCH_7A__
  176. +         movw r1, #:lower16:vgPlain_stats__n_xindirs_32
  177. +         movt r1, #:upper16:vgPlain_stats__n_xindirs_32
  178. ++#else
  179. ++        ldr  r1, =vgPlain_stats__n_xindirs_32
  180. ++#endif
  181. +         ldr  r2, [r1, #0]
  182. +         add  r2, r2, #1
  183. +         str  r2, [r1, #0]
  184. +        
  185. +         /* try a fast lookup in the translation cache */
  186. +         // r0 = next guest, r1,r2,r3,r4 scratch
  187. ++#ifdef __ARM_ARCH_7A__
  188. +         movw r1, #VG_TT_FAST_MASK       // r1 = VG_TT_FAST_MASK
  189. +         movw r4, #:lower16:VG_(tt_fast)
  190. ++#else
  191. ++        ldr  r1, =VG_TT_FAST_MASK
  192. ++#endif
  193. +
  194. +       and  r2, r1, r0, LSR #1         // r2 = entry #
  195. ++#ifdef __ARM_ARCH_7A__
  196. +         movt r4, #:upper16:VG_(tt_fast) // r4 = &VG_(tt_fast)
  197. ++#else
  198. ++        ldr  r4, =VG_(tt_fast)      // r4 = &VG_(tt_fast)
  199. ++#endif
  200. +
  201. +       add  r1, r4, r2, LSL #3         // r1 = &tt_fast[entry#]
  202. +
  203. ++#ifdef __ARM_ARCH_7A__
  204. +         ldrd r4, r5, [r1, #0]           // r4 = .guest, r5 = .host
  205. ++#else
  206. ++        ldr  r4, [r1, #0]           // r4 = .guest
  207. ++        ldr  r5, [r1, #4]           // r5 = .host
  208. ++#endif
  209. +
  210. +       cmp  r4, r0
  211. +
  212. +@@ -179,8 +225,12 @@
  213. +
  214. +         /* otherwise the fast lookup failed */
  215. +         /* RM ME -- stats only */
  216. ++#ifdef __ARM_ARCH_7A__
  217. +         movw r1, #:lower16:vgPlain_stats__n_xindir_misses_32
  218. +         movt r1, #:upper16:vgPlain_stats__n_xindir_misses_32
  219. ++#else
  220. ++        ldr  r1, =vgPlain_stats__n_xindir_misses_32
  221. ++#endif
  222. +         ldr  r2, [r1, #0]
  223. +         add  r2, r2, #1
  224. +         str  r2, [r1, #0]
  225. +diff -Naur valgrind-3.14.0/coregrind/m_machine.c valgrind-3.14.0-armv5/coregrind/m_machine.c
  226. +--- valgrind-3.14.0/coregrind/m_machine.c      2018-07-24 09:23:41.000000000 +0100
  227. ++++ valgrind-3.14.0-armv5/coregrind/m_machine.c        2019-01-04 17:58:37.416112114 +0000
  228. +@@ -456,6 +456,7 @@
  229. + #endif
  230. + #if defined(VGA_arm)
  231. + Int VG_(machine_arm_archlevel) = 4;
  232. ++UInt VG_(machine_arm_has_fpscr) = 0;
  233. + #endif
  234. +
  235. +
  236. +@@ -1540,7 +1541,7 @@
  237. +      vki_sigaction_fromK_t saved_sigill_act, saved_sigfpe_act;
  238. +      vki_sigaction_toK_t     tmp_sigill_act,   tmp_sigfpe_act;
  239. +
  240. +-     volatile Bool have_VFP, have_VFP2, have_VFP3, have_NEON, have_V8;
  241. ++     volatile Bool have_VFP, have_VFP2, have_VFP3, have_NEON, have_FPSCR, have_V8;
  242. +      volatile Int archlevel;
  243. +      Int r;
  244. +
  245. +@@ -1580,6 +1581,15 @@
  246. +      tmp_sigfpe_act.ksa_handler = handler_unsup_insn;
  247. +      VG_(sigaction)(VKI_SIGFPE, &tmp_sigfpe_act, NULL);
  248. +
  249. ++#if 1
  250. ++     have_VFP = False;
  251. ++     have_VFP2 = False;
  252. ++     have_VFP2 = False;
  253. ++     have_NEON = False;
  254. ++     have_FPSCR = False;
  255. ++     have_V8 = False;
  256. ++     archlevel = 5;
  257. ++#else
  258. +      /* VFP insns */
  259. +      have_VFP = True;
  260. +      if (VG_MINIMAL_SETJMP(env_unsup_insn)) {
  261. +@@ -1600,6 +1610,14 @@
  262. +         __asm__ __volatile__(".word 0xF2244154"); /* VMOV q2, q2 */
  263. +      }
  264. +
  265. ++     /* VFP2, VFP3, or SIMD Extension FPSCR register */
  266. ++     have_FPSCR = True;
  267. ++     if (VG_MINIMAL_SETJMP(env_unsup_insn)) {
  268. ++        have_FPSCR = False;
  269. ++     } else {
  270. ++        __asm__ __volatile__(".word 0xEEE12C10"); /* VMSR FPSCR, r2 */
  271. ++     }
  272. ++
  273. +      /* ARM architecture level */
  274. +      archlevel = 5; /* v5 will be base level */
  275. +      if (archlevel < 7) {
  276. +@@ -1631,18 +1649,20 @@
  277. +            archlevel = 8;
  278. +         }
  279. +      }
  280. +-
  281. ++#endif
  282. +      VG_(convert_sigaction_fromK_to_toK)(&saved_sigill_act, &tmp_sigill_act);
  283. +      VG_(convert_sigaction_fromK_to_toK)(&saved_sigfpe_act, &tmp_sigfpe_act);
  284. +      VG_(sigaction)(VKI_SIGILL, &tmp_sigill_act, NULL);
  285. +      VG_(sigaction)(VKI_SIGFPE, &tmp_sigfpe_act, NULL);
  286. +      VG_(sigprocmask)(VKI_SIG_SETMASK, &saved_set, NULL);
  287. +
  288. +-     VG_(debugLog)(1, "machine", "ARMv%d VFP %d VFP2 %d VFP3 %d NEON %d\n",
  289. ++     VG_(debugLog)(1, "machine",
  290. ++           "ARMv%d VFP %d VFP2 %d VFP3 %d NEON %d FPSCR %d\n",
  291. +            archlevel, (Int)have_VFP, (Int)have_VFP2, (Int)have_VFP3,
  292. +-           (Int)have_NEON);
  293. ++           (Int)have_NEON, (Int)have_FPSCR);
  294. +
  295. +      VG_(machine_arm_archlevel) = archlevel;
  296. ++     VG_(machine_arm_has_fpscr) = have_FPSCR;
  297. +
  298. +      va = VexArchARM;
  299. +      vai.endness = VexEndnessLE;
  300. +@@ -1652,6 +1672,7 @@
  301. +      if (have_VFP2) vai.hwcaps |= VEX_HWCAPS_ARM_VFP2;
  302. +      if (have_VFP)  vai.hwcaps |= VEX_HWCAPS_ARM_VFP;
  303. +      if (have_NEON) vai.hwcaps |= VEX_HWCAPS_ARM_NEON;
  304. ++     if (have_FPSCR) vai.hwcaps |= VEX_HWCAPS_ARM_FPSCR;
  305. +
  306. +      VG_(machine_get_cache_info)(&vai);
  307. +
  308. +diff -Naur valgrind-3.14.0/coregrind/m_scheduler/scheduler.c valgrind-3.14.0-armv5/coregrind/m_scheduler/scheduler.c
  309. +--- valgrind-3.14.0/coregrind/m_scheduler/scheduler.c  2018-09-30 05:41:00.000000000 +0100
  310. ++++ valgrind-3.14.0-armv5/coregrind/m_scheduler/scheduler.c    2019-01-04 17:58:37.417112109 +0000
  311. +@@ -1459,6 +1459,22 @@
  312. +                    && trc[0] != VG_TRC_CHAIN_ME_TO_FAST_EP);
  313. +       }
  314. +
  315. ++#     if defined(VGP_arm_linux)
  316. ++      /* This is a dirty, dirty hack. When a program jumps to the
  317. ++         location 0xFFFF0FE0 on linux, it's trying to read the
  318. ++         TLS. The reason we're able to put the check here is because
  319. ++         the fast cache will always miss when jumping to 0xFFFF0FE0
  320. ++         because it gets trapped here. The check could go in the
  321. ++         dispatcher, but ideally we can keep the check out of the fast
  322. ++         path.
  323. ++      */
  324. ++      if (VG_(get_IP)(tid) == 0xFFFF0FE0) {
  325. ++         trc[0] = VG_TRC_BORING;
  326. ++         VG_(set_IP)(tid, VG_(threads)[tid].arch.vex.guest_R14);
  327. ++         VG_(threads)[tid].arch.vex.guest_R0 = VG_(threads)[tid].arch.vex.guest_TPIDRURO;
  328. ++      }
  329. ++#     endif
  330. ++
  331. +       switch (trc[0]) {
  332. +       case VEX_TRC_JMP_BORING:
  333. +          /* assisted dispatch, no event.  Used by no-redir
  334. +diff -Naur valgrind-3.14.0/Makefile.all.am valgrind-3.14.0-armv5/Makefile.all.am
  335. +--- valgrind-3.14.0/Makefile.all.am    2018-07-14 05:58:40.000000000 +0100
  336. ++++ valgrind-3.14.0-armv5/Makefile.all.am      2019-01-04 17:58:37.414112124 +0000
  337. +@@ -206,11 +206,11 @@
  338. +
  339. + AM_FLAG_M3264_ARM_LINUX   = @FLAG_M32@
  340. + AM_CFLAGS_ARM_LINUX       = @FLAG_M32@ \
  341. +-                              $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
  342. ++                              $(AM_CFLAGS_BASE) -marm @FLAG_MCPU_CORTEX_A8@
  343. + AM_CFLAGS_PSO_ARM_LINUX   = @FLAG_M32@ $(AM_CFLAGS_BASE) \
  344. +-                              -marm -mcpu=cortex-a8 $(AM_CFLAGS_PSO_BASE)
  345. ++                              -marm @FLAG_MCPU_CORTEX_A8@ $(AM_CFLAGS_PSO_BASE)
  346. + AM_CCASFLAGS_ARM_LINUX    = @FLAG_M32@ \
  347. +-                              -marm -mcpu=cortex-a8 -g
  348. ++                              -marm @FLAG_MCPU_CORTEX_A8@ -g
  349. +
  350. + AM_FLAG_M3264_ARM64_LINUX = @FLAG_M64@
  351. + AM_CFLAGS_ARM64_LINUX     = @FLAG_M64@ $(AM_CFLAGS_BASE)
  352. +diff -Naur valgrind-3.14.0/memcheck/mc_main_asm.c valgrind-3.14.0-armv5/memcheck/mc_main_asm.c
  353. +--- valgrind-3.14.0/memcheck/mc_main_asm.c     2018-05-05 08:42:22.000000000 +0100
  354. ++++ valgrind-3.14.0-armv5/memcheck/mc_main_asm.c       2019-01-04 18:08:21.387216129 +0000
  355. +@@ -53,13 +53,29 @@
  356. + ".type   vgMemCheck_helperc_LOADV64le, %function \n"
  357. + "vgMemCheck_helperc_LOADV64le:          \n"
  358. + "      tst    r0, #7                    \n"
  359. ++#ifdef __ARM_ARCH_7A__
  360. + "      movw   r3, #:lower16:primary_map \n"
  361. ++#else
  362. ++"      ldr    r3, .LLV64LEpm            \n"
  363. ++#endif
  364. + "      bne    .LLV64LEc4                \n" // if misaligned
  365. + "      lsr    r2, r0, #16               \n"
  366. ++#ifdef __ARM_ARCH_7A__
  367. + "      movt   r3, #:upper16:primary_map \n"
  368. ++#endif
  369. + "      ldr    r2, [r3, r2, lsl #2]      \n"
  370. ++#ifdef __ARM_ARCH_7A__
  371. + "      uxth   r1, r0                    \n" // r1 is 0-(16)-0 X-(13)-X 000
  372. ++#else
  373. ++"      lsl    r1, r0, #16               \n"
  374. ++"      lsr    r1, r1, #16               \n"
  375. ++#endif
  376. ++#ifdef __ARM_ARCH_7A__
  377. + "      movw   r3, #0xAAAA               \n"
  378. ++#else
  379. ++"      mov    r3, #0xAA00               \n"
  380. ++"      orr    r3, r3, #0xAA             \n"
  381. ++#endif
  382. + "      lsr    r1, r1, #2                \n" // r1 is 0-(16)-0 00 X-(13)-X 0
  383. + "      ldrh   r1, [r2, r1]              \n"
  384. + "      cmp    r1, r3                    \n" // 0xAAAA == VA_BITS16_DEFINED
  385. +@@ -68,7 +84,12 @@
  386. + "      mov    r0, #0x0                  \n" // 0x0 == V_BITS32_DEFINED
  387. + "      bx     lr                        \n"
  388. + ".LLV64LEc0:                            \n"
  389. ++#ifdef __ARM_ARCH_7A__
  390. + "      movw   r3, #0x5555               \n"
  391. ++#else
  392. ++"      mov    r3, #0x5500               \n"
  393. ++"      orr    r3, r3, #0x55             \n"
  394. ++#endif
  395. + "      cmp    r1, r3                    \n" // 0x5555 == VA_BITS16_UNDEFINED
  396. + "      bne    .LLV64LEc4                \n" // if !all_undefined
  397. + "      mov    r1, #0xFFFFFFFF           \n" // 0xFFFFFFFF == V_BITS32_UNDEFINED
  398. +@@ -80,6 +101,10 @@
  399. + "      mov    r1, #64                   \n"
  400. + "      bl     mc_LOADVn_slow            \n"
  401. + "      pop    {r4, pc}                  \n"
  402. ++#ifndef __ARM_ARCH_7A__
  403. ++".LLV64LEpm:                            \n"
  404. ++"      .word primary_map                \n"
  405. ++#endif
  406. + ".size vgMemCheck_helperc_LOADV64le, .-vgMemCheck_helperc_LOADV64le \n"
  407. + ".previous\n"
  408. + );
  409. +@@ -135,12 +160,23 @@
  410. + ".type   vgMemCheck_helperc_LOADV32le, %function \n"
  411. + "vgMemCheck_helperc_LOADV32le:          \n"
  412. + "      tst    r0, #3                    \n" // 1
  413. ++#ifdef __ARM_ARCH_7A__
  414. + "      movw   r3, #:lower16:primary_map \n" // 1
  415. ++#else
  416. ++"      ldr    r3, .LLV32LEpm            \n"
  417. ++#endif
  418. + "      bne    .LLV32LEc4                \n" // 2  if misaligned
  419. + "      lsr    r2, r0, #16               \n" // 3
  420. ++#ifdef __ARM_ARCH_7A__
  421. + "      movt   r3, #:upper16:primary_map \n" // 3
  422. ++#endif
  423. + "      ldr    r2, [r3, r2, lsl #2]      \n" // 4
  424. ++#ifdef __ARM_ARCH_7A__
  425. + "      uxth   r1, r0                    \n" // 4
  426. ++#else
  427. ++"      lsl    r1, r0, #16               \n"
  428. ++"      lsr    r1, r1, #16               \n"
  429. ++#endif
  430. + "      ldrb   r1, [r2, r1, lsr #2]      \n" // 5
  431. + "      cmp    r1, #0xAA                 \n" // 6  0xAA == VA_BITS8_DEFINED
  432. + "      bne    .LLV32LEc0                \n" // 7  if !all_defined
  433. +@@ -157,6 +193,10 @@
  434. + "      mov    r1, #32                   \n"
  435. + "      bl     mc_LOADVn_slow            \n"
  436. + "      pop    {r4, pc}                  \n"
  437. ++#ifndef __ARM_ARCH_7A__
  438. ++".LLV32LEpm:                            \n"
  439. ++"      .word primary_map                \n"
  440. ++#endif
  441. + ".size vgMemCheck_helperc_LOADV32le, .-vgMemCheck_helperc_LOADV32le \n"
  442. + ".previous\n"
  443. + );
  444. +diff -Naur valgrind-3.14.0/memcheck/mc_main.c valgrind-3.14.0-armv5/memcheck/mc_main.c
  445. +--- valgrind-3.14.0/memcheck/mc_main.c 2018-09-30 05:41:00.000000000 +0100
  446. ++++ valgrind-3.14.0-armv5/memcheck/mc_main.c   2019-01-04 17:58:37.419112099 +0000
  447. +@@ -5193,9 +5193,20 @@
  448. + "      tst    r0, #1                    \n" //
  449. + "      bne    .LLV16LEc12               \n" // if misaligned
  450. + "      lsr    r2, r0, #16               \n" // r2 = pri-map-ix
  451. ++#ifdef __ARM_ARCH_7A__
  452. + "      movw   r3, #:lower16:primary_map \n" //
  453. ++#else
  454. ++"      ldr    r3, .LLV16LEpm            \n"
  455. ++#endif
  456. ++#ifdef __ARM_ARCH_7A__
  457. + "      uxth   r1, r0                    \n" // r1 = sec-map-offB
  458. ++#else
  459. ++"      lsl    r1, r0, #16               \n"
  460. ++"      lsr    r1, r1, #16               \n"
  461. ++#endif
  462. ++#ifdef __ARM_ARCH_7A__
  463. + "      movt   r3, #:upper16:primary_map \n" //
  464. ++#endif
  465. + "      ldr    r2, [r3, r2, lsl #2]      \n" // r2 = sec-map
  466. + "      ldrb   r1, [r2, r1, lsr #2]      \n" // r1 = sec-map-VABITS8
  467. + "      cmp    r1, #0xAA                 \n" // r1 == VA_BITS8_DEFINED?
  468. +@@ -5230,6 +5241,10 @@
  469. + "      mov    r1, #16                   \n" //
  470. + "      bl     mc_LOADVn_slow            \n" //
  471. + "      pop    {r4, pc}                  \n" //
  472. ++#ifndef __ARM_ARCH_7A__
  473. ++".LLV16LEpm:                            \n"
  474. ++"      .word primary_map                \n"
  475. ++#endif
  476. + ".size vgMemCheck_helperc_LOADV16le, .-vgMemCheck_helperc_LOADV16le \n"
  477. + ".previous\n"
  478. + );
  479. +@@ -5388,9 +5403,20 @@
  480. + ".type   vgMemCheck_helperc_LOADV8, %function \n"
  481. + "vgMemCheck_helperc_LOADV8:             \n" //
  482. + "      lsr    r2, r0, #16               \n" // r2 = pri-map-ix
  483. ++#ifdef __ARM_ARCH_7A__
  484. + "      movw   r3, #:lower16:primary_map \n" //
  485. ++#else
  486. ++"      ldr    r3, .LLV8LEpm             \n"
  487. ++#endif
  488. ++#ifdef __ARM_ARCH_7A__
  489. + "      uxth   r1, r0                    \n" // r1 = sec-map-offB
  490. ++#else
  491. ++"      lsl    r1, r0, #16               \n"
  492. ++"      lsr    r1, r1, #16               \n"
  493. ++#endif
  494. ++#ifdef __ARM_ARCH_7A__
  495. + "      movt   r3, #:upper16:primary_map \n" //
  496. ++#endif
  497. + "      ldr    r2, [r3, r2, lsl #2]      \n" // r2 = sec-map
  498. + "      ldrb   r1, [r2, r1, lsr #2]      \n" // r1 = sec-map-VABITS8
  499. + "      cmp    r1, #0xAA                 \n" // r1 == VA_BITS8_DEFINED?
  500. +@@ -5423,6 +5449,10 @@
  501. + "      mov    r1, #8                    \n" //
  502. + "      bl     mc_LOADVn_slow            \n" //
  503. + "      pop    {r4, pc}                  \n" //
  504. ++#ifndef __ARM_ARCH_7A__
  505. ++".LLV8LEpm:                             \n"
  506. ++"      .word primary_map                \n"
  507. ++#endif
  508. + ".size vgMemCheck_helperc_LOADV8, .-vgMemCheck_helperc_LOADV8 \n"
  509. + ".previous\n"
  510. + );
  511. +diff -Naur valgrind-3.14.0/VEX/priv/guest_arm_toIR.c valgrind-3.14.0-armv5/VEX/priv/guest_arm_toIR.c
  512. +--- valgrind-3.14.0/VEX/priv/guest_arm_toIR.c  2018-05-05 08:47:45.000000000 +0100
  513. ++++ valgrind-3.14.0-armv5/VEX/priv/guest_arm_toIR.c    2019-01-04 17:58:37.422112084 +0000
  514. +@@ -17548,27 +17548,39 @@
  515. +          /* Ok, now we're unconditional.  Generate a LL-SC loop. */
  516. +          assign(tRn, getIRegA(rN));
  517. +          assign(tNew, getIRegA(rM));
  518. +-         if (isB) {
  519. +-            /* swpb */
  520. +-            tOld = newTemp(Ity_I8);
  521. +-            stmt( IRStmt_LLSC(Iend_LE, tOld, mkexpr(tRn),
  522. +-                              NULL/*=>isLL*/) );
  523. +-            stmt( IRStmt_LLSC(Iend_LE, tSC1, mkexpr(tRn),
  524. +-                              unop(Iop_32to8, mkexpr(tNew))) );
  525. ++         if (VEX_ARM_ARCHLEVEL(archinfo->hwcaps) > 5) {
  526. ++             if (isB) {
  527. ++                /* swpb */
  528. ++                tOld = newTemp(Ity_I8);
  529. ++                stmt( IRStmt_LLSC(Iend_LE, tOld, mkexpr(tRn),
  530. ++                                  NULL/*=>isLL*/) );
  531. ++                stmt( IRStmt_LLSC(Iend_LE, tSC1, mkexpr(tRn),
  532. ++                                  unop(Iop_32to8, mkexpr(tNew))) );
  533. ++             } else {
  534. ++                /* swp */
  535. ++                tOld = newTemp(Ity_I32);
  536. ++                stmt( IRStmt_LLSC(Iend_LE, tOld, mkexpr(tRn),
  537. ++                                  NULL/*=>isLL*/) );
  538. ++                stmt( IRStmt_LLSC(Iend_LE, tSC1, mkexpr(tRn),
  539. ++                                  mkexpr(tNew)) );
  540. ++             }
  541. ++             stmt( IRStmt_Exit(unop(Iop_Not1, mkexpr(tSC1)),
  542. ++                               /*Ijk_NoRedir*/Ijk_Boring,
  543. ++                               IRConst_U32(guest_R15_curr_instr_notENC),
  544. ++                               OFFB_R15T ));
  545. ++             putIRegA(rD, isB ? unop(Iop_8Uto32, mkexpr(tOld)) : mkexpr(tOld),
  546. ++                          IRTemp_INVALID, Ijk_Boring);
  547. +          } else {
  548. +-            /* swp */
  549. +-            tOld = newTemp(Ity_I32);
  550. +-            stmt( IRStmt_LLSC(Iend_LE, tOld, mkexpr(tRn),
  551. +-                              NULL/*=>isLL*/) );
  552. +-            stmt( IRStmt_LLSC(Iend_LE, tSC1, mkexpr(tRn),
  553. +-                              mkexpr(tNew)) );
  554. ++            if (isB) {
  555. ++               putIRegA(rD, unop(Iop_8Uto32, loadLE(Ity_I8, mkexpr(tRn))),
  556. ++                       IRTemp_INVALID, Ijk_Boring);
  557. ++               storeLE(mkexpr(tRn), unop(Iop_32to8, mkexpr(tNew)));
  558. ++            } else {
  559. ++               putIRegA(rD, loadLE(Ity_I32, mkexpr(tRn)),
  560. ++                       IRTemp_INVALID, Ijk_Boring);
  561. ++               storeLE(mkexpr(tRn), mkexpr(tNew));
  562. ++            }
  563. +          }
  564. +-         stmt( IRStmt_Exit(unop(Iop_Not1, mkexpr(tSC1)),
  565. +-                           /*Ijk_NoRedir*/Ijk_Boring,
  566. +-                           IRConst_U32(guest_R15_curr_instr_notENC),
  567. +-                           OFFB_R15T ));
  568. +-         putIRegA(rD, isB ? unop(Iop_8Uto32, mkexpr(tOld)) : mkexpr(tOld),
  569. +-                      IRTemp_INVALID, Ijk_Boring);
  570. +          DIP("swp%s%s r%u, r%u, [r%u]\n",
  571. +              isB ? "b" : "", nCC(INSN_COND), rD, rM, rN);
  572. +          goto decode_success;
  573. +diff -Naur valgrind-3.14.0/VEX/priv/host_arm_defs.c valgrind-3.14.0-armv5/VEX/priv/host_arm_defs.c
  574. +--- valgrind-3.14.0/VEX/priv/host_arm_defs.c   2018-05-05 08:42:22.000000000 +0100
  575. ++++ valgrind-3.14.0-armv5/VEX/priv/host_arm_defs.c     2019-01-04 17:58:37.423112079 +0000
  576. +@@ -41,6 +41,8 @@
  577. + #include "host_generic_regs.h"
  578. + #include "host_arm_defs.h"
  579. +
  580. ++#include <stdio.h>
  581. ++
  582. + UInt arm_hwcaps = 0;
  583. +
  584. +
  585. +@@ -2991,10 +2993,10 @@
  586. + }
  587. +
  588. + /* Get an immediate into a register, using only that register, and
  589. +-   generating exactly 2 instructions, regardless of the value of the
  590. ++   generating exactly 2 or 4 instructions, regardless of the value of the
  591. +    immediate. This is used when generating sections of code that need
  592. +    to be patched later, so as to guarantee a specific size. */
  593. +-static UInt* imm32_to_ireg_EXACTLY2 ( UInt* p, Int rD, UInt imm32 )
  594. ++static UInt* imm32_to_iregNo_patchable ( UInt* p, Int rD, UInt imm32 )
  595. + {
  596. +    if (VEX_ARM_ARCHLEVEL(arm_hwcaps) > 6) {
  597. +       /* Generate movw rD, #low16 ;  movt rD, #high16. */
  598. +@@ -3010,14 +3012,33 @@
  599. +                        hi16 & 0xF);
  600. +       *p++ = instr;
  601. +    } else {
  602. +-      vassert(0); /* lose */
  603. ++      /* Generate mov rD,#X; orr rD,rD,#X; orr rD,rD,#X; orr rD,rD,#X */
  604. ++      UInt a = imm32 & 0xFF;
  605. ++      UInt b = (imm32 >> 8) & 0xFF;
  606. ++      UInt c = (imm32 >> 16) & 0xFF;
  607. ++      UInt d = (imm32 >> 24) & 0xFF;
  608. ++      UInt instr;
  609. ++      instr = XXXXXXXX(0xE, 0x3, 0xA, 0x0, rD, 0x0, (a >> 4) & 0xF, a & 0xF);
  610. ++//vex_printf("imm32_to_iregNo_patchable(%p, %d, 0x%x):", p, rD, imm32);
  611. ++//vex_printf(" 0x%08x", instr);
  612. ++      *p++ = instr;
  613. ++      instr = XXXXXXXX(0xE, 0x3, 0x8, rD, rD, 0xC, (b >> 4) & 0xF, b & 0xF);
  614. ++//vex_printf(" 0x%08x", instr);
  615. ++      *p++ = instr;
  616. ++      instr = XXXXXXXX(0xE, 0x3, 0x8, rD, rD, 0x8, (c >> 4) & 0xF, c & 0xF);
  617. ++//vex_printf(" 0x%08x", instr);
  618. ++      *p++ = instr;
  619. ++      instr = XXXXXXXX(0xE, 0x3, 0x8, rD, rD, 0x4, (d >> 4) & 0xF, d & 0xF);
  620. ++//vex_printf(" 0x%08x\n", instr);
  621. ++      *p++ = instr;
  622. ++      return p;
  623. +    }
  624. +    return p;
  625. + }
  626. +
  627. +-/* Check whether p points at a 2-insn sequence cooked up by
  628. +-   imm32_to_ireg_EXACTLY2(). */
  629. +-static Bool is_imm32_to_ireg_EXACTLY2 ( UInt* p, Int rD, UInt imm32 )
  630. ++/* Check whether p points at a sequence cooked up by
  631. ++   imm32_to_iregNo_patchable(). */
  632. ++static Bool is_imm32_to_iregNo_patchable ( UInt* p, Int rD, UInt imm32 )
  633. + {
  634. +    if (VEX_ARM_ARCHLEVEL(arm_hwcaps) > 6) {
  635. +       /* Generate movw rD, #low16 ;  movt rD, #high16. */
  636. +@@ -3032,10 +3053,34 @@
  637. +                     hi16 & 0xF);
  638. +       return p[0] == i0 && p[1] == i1;
  639. +    } else {
  640. +-      vassert(0); /* lose */
  641. ++      /* Generate mov rD,#X; orr rD,rD,#X; orr rD,rD,#X; orr rD,rD,#X */
  642. ++      UInt a = imm32 & 0xFF;
  643. ++      UInt b = (imm32 >> 8) & 0xFF;
  644. ++      UInt c = (imm32 >> 16) & 0xFF;
  645. ++      UInt d = (imm32 >> 24) & 0xFF;
  646. ++      UInt i0, i1, i2, i3;
  647. ++      i0 = XXXXXXXX(0xE, 0x3, 0xA, 0x0, rD, 0x0, (a >> 4) & 0xF, a & 0xF);
  648. ++      i1 = XXXXXXXX(0xE, 0x3, 0x8, rD, rD, 0xC, (b >> 4) & 0xF, b & 0xF);
  649. ++      i2 = XXXXXXXX(0xE, 0x3, 0x8, rD, rD, 0x8, (c >> 4) & 0xF, c & 0xF);
  650. ++      i3 = XXXXXXXX(0xE, 0x3, 0x8, rD, rD, 0x4, (d >> 4) & 0xF, d & 0xF);
  651. ++//vex_printf("is_imm32_to_iregNo_patchable(%p, %d, 0x%x):", p, rD, imm32);
  652. ++//vex_printf(" 0x%08x/0x%08x", p[0], i0);
  653. ++//vex_printf(" 0x%08x/0x%08x", p[1], i1);
  654. ++//vex_printf(" 0x%08x/0x%08x", p[2], i2);
  655. ++//vex_printf(" 0x%08x/0x%08x\n", p[3], i3);
  656. ++      return p[0] == i0 && p[1] == i1 && p[2] == i2 && p[3] == i3;
  657. +    }
  658. + }
  659. +
  660. ++/* Return the length of sequence cooked up by imm32_to_iregNo_patchable(). */
  661. ++static UInt imm32_to_iregNo_patchable_length ( void )
  662. ++{
  663. ++   if (VEX_ARM_ARCHLEVEL(arm_hwcaps) > 6) {
  664. ++      return 2;
  665. ++   } else {
  666. ++      return 4;
  667. ++   }
  668. ++}
  669. +
  670. + static UInt* do_load_or_store32 ( UInt* p,
  671. +                                   Bool isLoad, UInt rD, ARMAMode1* am )
  672. +@@ -3078,7 +3123,7 @@
  673. +                     const void* disp_cp_xassisted )
  674. + {
  675. +    UInt* p = (UInt*)buf;
  676. +-   vassert(nbuf >= 32);
  677. ++   vassert(nbuf >= 44);
  678. +    vassert(mode64 == False);
  679. +    vassert(0 == (((HWord)buf) & 3));
  680. +
  681. +@@ -3330,18 +3375,16 @@
  682. +          p = do_load_or_store32(p, False/*!isLoad*/,
  683. +                                 /*r*/12, i->ARMin.XDirect.amR15T);
  684. +
  685. ++//vex_printf("ARMin_XDirect\n");
  686. ++
  687. +          /* --- FIRST PATCHABLE BYTE follows --- */
  688. +          /* VG_(disp_cp_chain_me_to_{slowEP,fastEP}) (where we're
  689. +             calling to) backs up the return address, so as to find the
  690. +-            address of the first patchable byte.  So: don't change the
  691. +-            number of instructions (3) below. */
  692. +-         /* movw r12, lo16(VG_(disp_cp_chain_me_to_{slowEP,fastEP})) */
  693. +-         /* movt r12, hi16(VG_(disp_cp_chain_me_to_{slowEP,fastEP})) */
  694. +-         /* blx  r12  (A1) */
  695. ++            address of the first patchable byte. */
  696. +          const void* disp_cp_chain_me
  697. +                   = i->ARMin.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP
  698. +                                               : disp_cp_chain_me_to_slowEP;
  699. +-         p = imm32_to_ireg_EXACTLY2(p, /*r*/12,
  700. ++         p = imm32_to_iregNo_patchable(p, /*r*/12,
  701. +                                     (UInt)(Addr)disp_cp_chain_me);
  702. +          *p++ = 0xE12FFF3C;
  703. +          /* --- END of PATCHABLE BYTES --- */
  704. +@@ -3349,7 +3392,7 @@
  705. +          /* Fix up the conditional jump, if there was one. */
  706. +          if (i->ARMin.XDirect.cond != ARMcc_AL) {
  707. +             Int delta = (UChar*)p - (UChar*)ptmp; /* must be signed */
  708. +-            vassert(delta > 0 && delta < 40);
  709. ++            vassert(delta > 0 && delta < 48);
  710. +             vassert((delta & 3) == 0);
  711. +             UInt notCond = 1 ^ (UInt)i->ARMin.XDirect.cond;
  712. +             vassert(notCond <= 13); /* Neither AL nor NV */
  713. +@@ -3552,11 +3595,14 @@
  714. +             /* Do the 'else' actions */
  715. +             switch (i->ARMin.Call.rloc.pri) {
  716. +                case RLPri_Int:
  717. +-                  p = imm32_to_ireg_EXACTLY2(p, /*r*/0, 0x55555555);
  718. ++//vex_printf("ARMin_Call/RLPri_Int\n");
  719. ++                  p = imm32_to_iregNo_patchable(p, /*r*/0, 0x55555555);
  720. +                   break;
  721. +                case RLPri_2Int:
  722. ++//vex_printf("ARMin_Call/RLPri_Int2\n");
  723. ++                  p = imm32_to_iregNo_patchable(p, /*r*/0, 0x55555555);
  724. +                   vassert(0); //ATC
  725. +-                  p = imm32_to_ireg_EXACTLY2(p, /*r*/0, 0x55555555);
  726. ++                  p = imm32_to_iregNo_patchable(p, /*r*/0, 0x55555555);
  727. +                   /* mov r1, r0 */
  728. +                   *p++ = 0xE1A01000;
  729. +                   break;
  730. +@@ -4856,7 +4902,8 @@
  731. +             adc  r11, r11, #0
  732. +             str  r11, [r12+4]
  733. +          */
  734. +-         p = imm32_to_ireg_EXACTLY2(p, /*r*/12, 0x65556555);
  735. ++//vex_printf("ARMin_ProfInc\n");
  736. ++         p = imm32_to_iregNo_patchable(p, /*r*/12, 0x65556555);
  737. +          *p++ = 0xE59CB000;
  738. +          *p++ = 0xE29BB001;
  739. +          *p++ = 0xE58CB000;
  740. +@@ -4880,7 +4927,8 @@
  741. +    /*NOTREACHED*/
  742. +
  743. +   done:
  744. +-   vassert(((UChar*)p) - &buf[0] <= 32);
  745. ++//vex_printf("tag %d len %d\n", i->tag, ((UChar*)p) - &buf[0]);
  746. ++   vassert(((UChar*)p) - &buf[0] <= 44);
  747. +    return ((UChar*)p) - &buf[0];
  748. + }
  749. +
  750. +@@ -4903,34 +4951,50 @@
  751. + {
  752. +    vassert(endness_host == VexEndnessLE);
  753. +
  754. +-   /* What we're expecting to see is:
  755. ++   /* What we're expecting to see is (>=ARMv7):
  756. +         movw r12, lo16(disp_cp_chain_me_to_EXPECTED)
  757. +         movt r12, hi16(disp_cp_chain_me_to_EXPECTED)
  758. +         blx  r12
  759. ++      or (<=ARMv6):
  760. ++        mov  r12, #...
  761. ++        orr  r12, r12, #...
  762. ++        orr  r12, r12, #...
  763. ++        orr  r12, r12, #...
  764. ++        blx  r12
  765. +       viz
  766. +-        <8 bytes generated by imm32_to_ireg_EXACTLY2>
  767. ++        <code generated by imm32_to_iregNo_patchable>
  768. +         E1 2F FF 3C
  769. +    */
  770. +    UInt* p = (UInt*)place_to_chain;
  771. ++   UInt  insn_len = imm32_to_iregNo_patchable_length();
  772. +    vassert(0 == (3 & (HWord)p));
  773. +-   vassert(is_imm32_to_ireg_EXACTLY2(
  774. ++   vassert(is_imm32_to_iregNo_patchable(
  775. +               p, /*r*/12, (UInt)(Addr)disp_cp_chain_me_EXPECTED));
  776. +-   vassert(p[2] == 0xE12FFF3C);
  777. ++   vassert(p[insn_len] == 0xE12FFF3C);
  778. +    /* And what we want to change it to is either:
  779. +-        (general case)
  780. ++        (general case, >=ARMv7)
  781. +           movw r12, lo16(place_to_jump_to)
  782. +           movt r12, hi16(place_to_jump_to)
  783. +           bx   r12
  784. ++        or (<=ARMv6)
  785. ++          mov  r12, #...
  786. ++          orr  r12, r12, #...
  787. ++          orr  r12, r12, #...
  788. ++          orr  r12, r12, #...
  789. +         viz
  790. +-          <8 bytes generated by imm32_to_ireg_EXACTLY2>
  791. ++          <code generated by imm32_to_iregNo_patchable>
  792. +           E1 2F FF 1C
  793. +       ---OR---
  794. +         in the case where the displacement falls within 26 bits
  795. +-          b disp24; undef; undef
  796. ++          b disp24; undef; undef (>=ARMv7)
  797. ++        or
  798. ++          b disp24; undef; undef; undef; undef (<=ARMv6)
  799. +         viz
  800. +           EA <3 bytes == disp24>
  801. +           FF 00 00 00
  802. +           FF 00 00 00
  803. ++          (FF 00 00 00)
  804. ++          (FF 00 00 00)
  805. +
  806. +       In both cases the replacement has the same length as the original.
  807. +       To remain sane & verifiable,
  808. +@@ -4945,6 +5009,8 @@
  809. +    /* This is the delta we need to put into a B insn.  It's relative
  810. +       to the start of the next-but-one insn, hence the -8.  */
  811. +    Long delta   = (Long)((const UChar *)place_to_jump_to - (const UChar*)p) - 8;
  812. ++//vex_printf("chainXDirect_ARM\n");
  813. ++//vex_printf("place_to_chain=%p, place_to_jump_to=%p, delta=%d, insn_len=%d\n", p, place_to_jump_to, delta, insn_len);
  814. +    Bool shortOK = delta >= -30*1000*1000 && delta < 30*1000*1000;
  815. +    vassert(0 == (delta & (Long)3));
  816. +
  817. +@@ -4969,13 +5035,17 @@
  818. +       p[0] = 0xEA000000 | (simm24 & 0x00FFFFFF);
  819. +       p[1] = 0xFF000000;
  820. +       p[2] = 0xFF000000;
  821. ++      if (insn_len == 4) {
  822. ++         p[3] = 0xFF000000;
  823. ++         p[4] = 0xFF000000;
  824. ++      }
  825. +    } else {
  826. +-      (void)imm32_to_ireg_EXACTLY2(
  827. ++      (void)imm32_to_iregNo_patchable(
  828. +                p, /*r*/12, (UInt)(Addr)place_to_jump_to);
  829. +-      p[2] = 0xE12FFF1C;
  830. ++      p[insn_len] = 0xE12FFF1C;
  831. +    }
  832. +
  833. +-   VexInvalRange vir = {(HWord)p, 12};
  834. ++   VexInvalRange vir = {(HWord)p, (insn_len+1) * 4};
  835. +    return vir;
  836. + }
  837. +
  838. +@@ -4990,33 +5060,47 @@
  839. +    vassert(endness_host == VexEndnessLE);
  840. +
  841. +    /* What we're expecting to see is:
  842. +-        (general case)
  843. ++        (general case, >=ARMv7)
  844. +           movw r12, lo16(place_to_jump_to_EXPECTED)
  845. +           movt r12, lo16(place_to_jump_to_EXPECTED)
  846. +           bx   r12
  847. ++        or (<=ARMv6):
  848. ++          mov  r12, #...
  849. ++          orr  r12, r12, #...
  850. ++          orr  r12, r12, #...
  851. ++          orr  r12, r12, #...
  852. ++          bx   r12
  853. +         viz
  854. +-          <8 bytes generated by imm32_to_ireg_EXACTLY2>
  855. ++          <code bytes generated by imm32_to_iregNo_patchable>
  856. +           E1 2F FF 1C
  857. +       ---OR---
  858. +         in the case where the displacement falls within 26 bits
  859. +-          b disp24; undef; undef
  860. ++          b disp24; undef; undef (>=ARMv7)
  861. ++        or
  862. ++          b disp24; undef; undef; undef; undef (<=ARMv6)
  863. +         viz
  864. +           EA <3 bytes == disp24>
  865. +           FF 00 00 00
  866. +           FF 00 00 00
  867. ++          (FF 00 00 00)
  868. ++          (FF 00 00 00)
  869. +    */
  870. +    UInt* p = (UInt*)place_to_unchain;
  871. ++   UInt  insn_len = imm32_to_iregNo_patchable_length();
  872. +    vassert(0 == (3 & (HWord)p));
  873. +
  874. ++//vex_printf("unchainXDirect_ARM\n");
  875. ++//vex_printf("place_to_unchain=%p place_to_jump_to_EXPECTED=%p\n", place_to_unchain, place_to_jump_to_EXPECTED);
  876. +    Bool valid = False;
  877. +-   if (is_imm32_to_ireg_EXACTLY2(
  878. ++   if (is_imm32_to_iregNo_patchable(
  879. +           p, /*r*/12, (UInt)(Addr)place_to_jump_to_EXPECTED)
  880. +-       && p[2] == 0xE12FFF1C) {
  881. ++       && p[insn_len] == 0xE12FFF1C) {
  882. +       valid = True; /* it's the long form */
  883. +       if (0)
  884. +          vex_printf("QQQ unchainXDirect_ARM: found long form\n");
  885. +    } else
  886. +-   if ((p[0] >> 24) == 0xEA && p[1] == 0xFF000000 && p[2] == 0xFF000000) {
  887. ++   if ((p[0] >> 24) == 0xEA && p[1] == 0xFF000000 && p[2] == 0xFF000000 &&
  888. ++      (insn_len == 2 || (p[3] == 0xFF000000 && p[4] == 0xFF000000))) {
  889. +       /* It's the short form.  Check the displacement is right. */
  890. +       Int simm24 = p[0] & 0x00FFFFFF;
  891. +       simm24 <<= 8; simm24 >>= 8;
  892. +@@ -5031,15 +5115,21 @@
  893. +    /* And what we want to change it to is:
  894. +         movw r12, lo16(disp_cp_chain_me)
  895. +         movt r12, hi16(disp_cp_chain_me)
  896. +-        blx  r12
  897. ++        bx   r12
  898. ++      or
  899. ++        mov  r12, #...
  900. ++        orr  r12, r12, #...
  901. ++        orr  r12, r12, #...
  902. ++        orr  r12, r12, #...
  903. ++        bx   r12
  904. +       viz
  905. +-        <8 bytes generated by imm32_to_ireg_EXACTLY2>
  906. ++        <code generated by imm32_to_iregNo_patchable>
  907. +         E1 2F FF 3C
  908. +    */
  909. +-   (void)imm32_to_ireg_EXACTLY2(
  910. ++   (void)imm32_to_iregNo_patchable(
  911. +             p, /*r*/12, (UInt)(Addr)disp_cp_chain_me);
  912. +-   p[2] = 0xE12FFF3C;
  913. +-   VexInvalRange vir = {(HWord)p, 12};
  914. ++   p[insn_len] = 0xE12FFF3C;
  915. ++   VexInvalRange vir = {(HWord)p, (insn_len+1) * 4};
  916. +    return vir;
  917. + }
  918. +
  919. +@@ -5053,16 +5143,17 @@
  920. +    vassert(endness_host == VexEndnessLE);
  921. +    vassert(sizeof(ULong*) == 4);
  922. +    UInt* p = (UInt*)place_to_patch;
  923. ++   UInt  insn_len = imm32_to_iregNo_patchable_length();
  924. +    vassert(0 == (3 & (HWord)p));
  925. +-   vassert(is_imm32_to_ireg_EXACTLY2(p, /*r*/12, 0x65556555));
  926. +-   vassert(p[2] == 0xE59CB000);
  927. +-   vassert(p[3] == 0xE29BB001);
  928. +-   vassert(p[4] == 0xE58CB000);
  929. +-   vassert(p[5] == 0xE59CB004);
  930. +-   vassert(p[6] == 0xE2ABB000);
  931. +-   vassert(p[7] == 0xE58CB004);
  932. +-   imm32_to_ireg_EXACTLY2(p, /*r*/12, (UInt)(Addr)location_of_counter);
  933. +-   VexInvalRange vir = {(HWord)p, 8};
  934. ++   vassert(is_imm32_to_iregNo_patchable(p, /*r*/12, 0x65556555));
  935. ++   vassert(p[insn_len] == 0xE59CB000);
  936. ++   vassert(p[insn_len+1] == 0xE29BB001);
  937. ++   vassert(p[insn_len+2] == 0xE58CB000);
  938. ++   vassert(p[insn_len+3] == 0xE59CB004);
  939. ++   vassert(p[insn_len+4] == 0xE2ABB000);
  940. ++   vassert(p[insn_len+5] == 0xE58CB004);
  941. ++   imm32_to_iregNo_patchable(p, /*r*/12, (UInt)(Addr)location_of_counter);
  942. ++   VexInvalRange vir = {(HWord)p, insn_len * 4};
  943. +    return vir;
  944. + }
  945. +
  946. +diff -Naur valgrind-3.14.0/VEX/pub/libvex.h valgrind-3.14.0-armv5/VEX/pub/libvex.h
  947. +--- valgrind-3.14.0/VEX/pub/libvex.h   2018-07-24 09:23:41.000000000 +0100
  948. ++++ valgrind-3.14.0-armv5/VEX/pub/libvex.h     2019-01-04 17:58:37.424112074 +0000
  949. +@@ -186,6 +186,7 @@
  950. + #define VEX_HWCAPS_ARM_VFP    (1<<6)  /* VFP extension */
  951. + #define VEX_HWCAPS_ARM_VFP2   (1<<7)  /* VFPv2 */
  952. + #define VEX_HWCAPS_ARM_VFP3   (1<<8)  /* VFPv3 */
  953. ++#define VEX_HWCAPS_ARM_FPSCR  (1<<9)  /* FPSCR register (VFPv2,v3 or NEON) */
  954. + /* Bits 15:10 reserved for (possible) future VFP revisions */
  955. + #define VEX_HWCAPS_ARM_NEON   (1<<16) /* Advanced SIMD also known as NEON */
  956. +
  957. diff --git a/ptxdist/patches/valgrind-3.14.0/autogen.sh b/ptxdist/patches/valgrind-3.14.0/autogen.sh
  958. new file mode 100755
  959. index 0000000..1e5ea4d
  960. --- /dev/null
  961. +++ b/ptxdist/patches/valgrind-3.14.0/autogen.sh
  962. @@ -0,0 +1,21 @@
  963. +#!/bin/ksh93
  964. +
  965. +# gisburn: do not set PATH, we need to inhert the custom PATH
  966. +# from caller for crosscompile environments
  967. +
  968. +set -o errexit
  969. +
  970. +aclocal $ACLOCAL_FLAGS
  971. +
  972. +libtoolize \
  973. +       --force \
  974. +       --copy
  975. +
  976. +autoreconf \
  977. +       --force \
  978. +       --install \
  979. +       --warnings=cross \
  980. +       --warnings=syntax \
  981. +       --warnings=obsolete \
  982. +       --warnings=unsupported
  983. +# EOF.
  984. diff --git a/ptxdist/patches/valgrind-3.14.0/series b/ptxdist/patches/valgrind-3.14.0/series
  985. new file mode 100644
  986. index 0000000..fdd933c
  987. --- /dev/null
  988. +++ b/ptxdist/patches/valgrind-3.14.0/series
  989. @@ -0,0 +1 @@
  990. +0001-valgrind3140-armv5tejl-support.patch
  991. diff --git a/ptxdist/rules/valgrind.in b/ptxdist/rules/valgrind.in
  992. new file mode 100644
  993. index 0000000..e49ff57
  994. --- /dev/null
  995. +++ b/ptxdist/rules/valgrind.in
  996. @@ -0,0 +1,16 @@
  997. +## SECTION=debug_tools
  998. +
  999. +config VALGRIND
  1000. +       tristate
  1001. +       prompt "valgrind"
  1002. +       help
  1003. +         A memory debugger and profiler
  1004. +
  1005. +         Valgrind is a GPL'd system for debugging and profiling
  1006. +         x86-Linux programs. With Valgrind's tool suite you can
  1007. +         automatically detect many memory management and threading
  1008. +         bugs, avoiding hours of frustrating bug-hunting, making your
  1009. +         programs more stable. You can also perform detailed
  1010. +         profiling to help speed up your programs.  For more info,
  1011. +         check: http://valgrind.org/
  1012. +
  1013. diff --git a/ptxdist/rules/valgrind.make b/ptxdist/rules/valgrind.make
  1014. new file mode 100644
  1015. index 0000000..2d4c1da
  1016. --- /dev/null
  1017. +++ b/ptxdist/rules/valgrind.make
  1018. @@ -0,0 +1,94 @@
  1019. +# -*-makefile-*-
  1020. +#
  1021. +# Copyright (C) 2005 by Shahar Livne <shahar@livnex.com>
  1022. +#               2008, 2009 by Marc Kleine-Budde <mkl@pengutronix.de>
  1023. +#              2019 by Roland Mainz <roland.mainz@nrubsig.org>
  1024. +#
  1025. +# See CREDITS for details about who has contributed to this project.
  1026. +#
  1027. +# For further information about the PTXdist project and license conditions
  1028. +# see the README file.
  1029. +#
  1030. +
  1031. +#
  1032. +# See ptxdist/patches/valgrind-3.14.0/0001-valgrind3140-armv5tejl-support.patch
  1033. +# for patch which provides ARMv5 support (including armv5tejl)
  1034. +#
  1035. +
  1036. +#
  1037. +# We provide this package
  1038. +#
  1039. +PACKAGES-$(PTXCONF_ARCH_X86)-$(PTXCONF_VALGRIND) += valgrind
  1040. +PACKAGES-$(PTXCONF_ARCH_PPC)-$(PTXCONF_VALGRIND) += valgrind
  1041. +PACKAGES-$(PTXCONF_ARCH_ARM)-$(PTXCONF_VALGRIND) += valgrind
  1042. +
  1043. +#
  1044. +# Paths and names
  1045. +#
  1046. +VALGRIND_VERSION       := 3.14.0
  1047. +VALGRIND_MD5           := 74175426afa280184b62591b58c671b3
  1048. +VALGRIND               := valgrind-$(VALGRIND_VERSION)
  1049. +VALGRIND_SUFFIX                := tar.bz2
  1050. +VALGRIND_URL           := http://valgrind.org/downloads/$(VALGRIND).$(VALGRIND_SUFFIX)
  1051. +VALGRIND_SOURCE                := $(SRCDIR)/$(VALGRIND).$(VALGRIND_SUFFIX)
  1052. +VALGRIND_DIR           := $(BUILDDIR)/$(VALGRIND)
  1053. +VALGRIND_LICENSE       := GPLv2
  1054. +
  1055. +# ----------------------------------------------------------------------------
  1056. +# Prepare
  1057. +# ----------------------------------------------------------------------------
  1058. +
  1059. +ifdef KERNEL_VERSION
  1060. +VALGRIND_KERNEL_VERSION := $(KERNEL_VERSION)
  1061. +endif
  1062. +
  1063. +ifdef KERNEL_HEADER_VERSION
  1064. +VALGRIND_KERNEL_VERSION := $(KERNEL_HEADER_VERSION)
  1065. +endif
  1066. +
  1067. +VALGRIND_PATH  := PATH=$(CROSS_PATH)
  1068. +VALGRIND_ENV   := \
  1069. +       $(CROSS_ENV) \
  1070. +       valgrind_cv_sys_kernel_version=$(VALGRIND_KERNEL_VERSION)
  1071. +
  1072. +#
  1073. +# autoconf
  1074. +#
  1075. +# See also custom ptxdist/patches/valgrind-3.14.0/autogen.sh
  1076. +#
  1077. +VALGRIND_CONF_TOOL := autoconf
  1078. +VALGRIND_CONF_OPT  := \
  1079. +       $(CROSS_AUTOCONF_USR) \
  1080. +       --enable-tls
  1081. +
  1082. +# ----------------------------------------------------------------------------
  1083. +# Target-Install
  1084. +# ----------------------------------------------------------------------------
  1085. +
  1086. +$(STATEDIR)/valgrind.targetinstall:
  1087. +       @$(call targetinfo)
  1088. +
  1089. +       @$(call install_init, valgrind)
  1090. +       @$(call install_fixup, valgrind,PRIORITY,optional)
  1091. +       @$(call install_fixup, valgrind,SECTION,base)
  1092. +       @$(call install_fixup, valgrind,AUTHOR,"Roland Mainz <roland.mainz@nrubsig.org>")
  1093. +       @$(call install_fixup, valgrind,DESCRIPTION,missing)
  1094. +
  1095. +       @$(call install_copy, valgrind, 0, 0, 0755, -, /usr/bin/valgrind)
  1096. +
  1097. +       @cd $(VALGRIND_PKGDIR) && \
  1098. +               find usr/lib/valgrind -name "*.supp" -o -name "*.so" | while read file; do \
  1099. +               $(call install_copy, valgrind, 0, 0, 0644, -, /$$file, n) \
  1100. +       done
  1101. +
  1102. +       @cd $(VALGRIND_PKGDIR) && \
  1103. +               find usr/lib/valgrind -type f \
  1104. +                       \! -wholename "*.a" \! -wholename "*.supp" \! -wholename "*.so" | while read file; do \
  1105. +               $(call install_copy, valgrind, 0, 0, 0755, -, /$$file) \
  1106. +       done
  1107. +
  1108. +       @$(call install_finish, valgrind)
  1109. +
  1110. +       @$(call touch)
  1111. +
  1112. +# vim: syntax=make
  1113. --
  1114. 1.9.1

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